Fundamentals of Computer Organization and Architecture & Advanced Computer Architecture and Parallel Processing, 2 Volume Set

1. Auflage 2005
ISBN: 978-0-471-70380-8
Verlag: Wiley

Buch, Englisch, 576 Seiten, Format (B × H): 163 mm x 242 mm, Gewicht: 1046 g

This two-volume set provides comprehensive coverage of the field of computer organization and architecture.

The first book in the set gives complete coverage of the subjects pertaining to introductory courses in computer organization and architecture, including:

- Instruction set architecture and design
- Assembly language programming
- Computer arithmetic
- Processing unit design
- Memory system design
- Input-output design and organization
- Pipelining design techniques
- Reduced Instruction Set Computers (RISCs)

The second volume provides advanced coverage of the field. Both books benefit from the authors' many years’ experience in teaching this field as they offer real world applications, examples of machines, case studies and practical experiences in each chapter.

Autoren/Hrsg.

Abd-El-Barr, Mostafa

El-Rewini, Hesham

Inhaltsverzeichnis

Fundamentals of Computer Organization and Architecture

Preface xi

1. Introduction to Computer Systems 1
1.1. Historical Background 2
1.2. Architectural Development and Styles 4
1.3. Technological Development 5
1.4. Performance Measures 6
1.5. Summary 11

2. Instruction Set Architecture and Design 15
2.1. Memory Locations and Operations 15
2.2. Addressing Modes 18
2.3. Instruction Types 26
2.4. Programming Examples 31
2.5. Summary 33

3. Assembly Language Programming 37
3.1. A Simple Machine 38
3.2. Instructions Mnemonics and Syntax 40
3.3. Assembler Directives and Commands 43
3.4. Assembly and Execution of Programs 44
3.5. Example: The X86 Family 47
3.6. Summary 55

4. Computer Arithmetic 59
4.1. Number Systems 59
4.2. Integer Arithmetic 63
4.3. Floating-Point Arithmetic 74
4.4. Summary 79

5. Processing Unit Design 83
5.1. CPU Basics 83
5.2. Register Set 85
5.3. Datapath 89
5.4. CPU Instruction Cycle 91
5.5. Control Unit 95
5.6. Summary 104

6. Memory System Design I 107
6.1. Basic Concepts 107
6.2. Cache Memory 109
6.3. Summary 130

7. Memory System Design II 135
7.1.Main Memory 135
7.2. Virtual Memory 142
7.3. Read-Only Memory 156
7.4. Summary 158

8. Input–Output Design and Organization 161
8.1. Basic Concepts 162
8.2. Programmed I/O 164
8.3. Interrupt-Driven I/O 167
8.4. Direct Memory Access (DMA) 175
8.5. Buses 177
8.6. Input–Output Interfaces 181
8.7. Summary 182

9 Pipelining Design Techniques 185
9.1. General Concepts 185
9.2. Instruction Pipeline 187
9.3. Example Pipeline Processors 201
9.4. Instruction-Level Parallelism 207
9.5. Arithmetic Pipeline 209
9.6. Summary 213

10 Reduced Instruction Set Computers (RISCs) 215
10.1. RISC/CISC Evolution Cycle 217
10.2. RISCs Design Principles 218
10.3. Overlapped Register Windows 220
10.4. RISCs Versus CISCs 221
10.5. Pioneer (University) RISC Machines 223
10.6. Example of Advanced RISC Machines 227
10.7. Summary 232

11 Introduction to Multiprocessors 235
11.1. Introduction 235
11.2. Classification of Computer Architectures 236
11.3. SIMD Schemes 244
11.4. MIMD Schemes 246
11.5. Interconnection Networks 252
11.6. Analysis and Performance Metrics 254
11.7. Summary 254

Exercises 255
References and Further Reading 256
Index 259

Advanced Computer Architecture and Parallel Processing

1. Introduction to Advanced Computer Architecture and Parallel Processing 1
1.1 Four Decades of Computing 2
1.2 Flynn's Taxonomy of Computer Architecture 4
1.3 SIMD Architecture 5
1.4 MIMD Architecture 6
1.5 Interconnection Networks 11
1.6 Chapter Summary 15

2. Multiprocessors Interconnection Networks 19

2.1 Interconnection Networks Taxonomy 19
2.2 Bus-Based Dynamic Interconnection Networks 20
2.3 Switch-Based Interconnection Networks 24
2.4 Static Interconnection Networks 33
2.5 Analysis and Performance Metrics 41
2.6 Chapter Summary 45

3. Performance Analysis of Multiprocessor Architecture 51
3.1 Computational Models 51
3.2 An Argument for Parallel Architectures 55
3.3 Interconnection Networks Performance Issues 58
3.4 Scalability of Parallel Architectures 63
3.5 Benchmark Performance 67
3.6 Chapter Summary 72

4. Shared Memory Architecture 77
4.1 Classification of Shared Memory Systems 78
4.2 Bus-Based Symmetric Multiprocessors 80
4.3 Basic Cache Coherency Methods 81
4.4 Snooping Protocols 83
4.5 Directory Based Protocols 89
4.6 Shared Memory Programming 96
4.7 Chapter Summary 99

5. Message Passing Architecture 103
5.1 Introduction to Message Passing 103
5.2 Routing in Message Passing Networks 105
5.3 Switching Mechanisms in Message Passing 109
5.4 Message Passing Programming Models 114
5.5 Processor Support for Message Passing 117
5.6 Example Message Passing Architectures 118
5.7 Message Passing Versus Shared Memory Architectures 122
5.8 Chapter Summary 123

6. Abstract Models 127
6.1 The PRAM Model and Its Variations 127
6.2 Simulating Multiple Accesses on an EREW PRAM 129
6.3 Analysis of Parallel Algorithms 131
6.4 Computing Sum and All Sums 133
6.5 Matrix Multiplication 136
6.6 Sorting 139
6.7 Message Passing Model 140
6.8 Leader Election Problem 146
6.9 Leader Election in Synchronous Rings 147
6.10 Chapter Summary 154

7. Network Computing 157
7.1 Computer Networks Basics 158
7.2 Client/Server Systems 161
7.3 Clusters 166
7.4 Interconnection Networks 170
7.5 Cluster Examples 175
7.6 Grid Computing 177
7.7 Chapter Summary 178

8. Parallel Programming in the Parallel Virtual Machine 181
8.1 PVM Environment and Application Structure 181
8.2 Task Creation 185
8.3 Task Groups 188
8.4 Communication Among Tasks 190
8.5 Task Synchronization 196
8.6 Reduction Operations 198
8.7 Work Assignment 200
8.8 Chapter Summary 201

9. Message Passing Interface (MPI) 205
9.1 Communicators 205
9.2 Virtual Topologies 209
9.3 Task Communication 213
9.4 Synchronization 217
9.5 Collective Operations 220
9.6 Task Creation 225
9.7 One-Sided Communication 228
9.8 Chapter Summary 231

10 Scheduling and Task Allocation 235
10.1 The Scheduling Problem 235
10.2 Scheduling DAGs without Considering Communication 238
10.3 Communication Models 242
10.4 Scheduling DAGs with Communication 244
10.5 The NP-Completeness of the Scheduling Problem 248
10.6 Heuristic Algorithms 250
10.7 Task Allocation 256
10.8 Scheduling in Heterogeneous Environments 262

Problems 263
References 264
Index 267

Über Autor(innen)

MOSTAFA ABD-EL-BARR, PhD, is currently a professor and chairman of the Department of Information Science at Kuwait University. He has co-authored two other books, published more than 120 papers, and served as chair for a number of international conferences and symposia.

HESHAM EL-REWINI, PhD, PE, is a full professor and chairman of the Department of Computer Sciences and Engineering at Southern Methodist University (SMU). He has co-authored several books, published numerous research papers in journals and conference proceedings, and chaired many international conferences.