Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors

Erscheinungsjahr 2014
ISBN: 978-3-319-06339-3
Verlag: Springer

Buch, Englisch, 94 Seiten, Format (B × H): 160 mm x 241 mm, Gewicht: 342 g

This book describes fault tolerance techniques based on software and hardware to create hybrid techniques. They are able to reduce overall performance degradation and increase error detection when associated with applications implemented in embedded processors.  Coverage begins with an extensive discussion of the current state-of-the-art in fault tolerance techniques.  The authors then discuss the best trade-off between software-based and hardware-based techniques and introduce novel hybrid techniques. Proposed techniques increase existing fault detection rates up to 100%, while maintaining low performance overheads in area and application execution time.

Zielgruppe

Research

Autoren/Hrsg.

Azambuja, José Rodrigo

Kastensmidt, Fernanda

Becker, Jürgen

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Mikroprozessoren
• Mathematik | Informatik EDV | Informatik Technische Informatik Eingebettete Systeme

Inhaltsverzeichnis

Introduction.- Background.- Fault Tolerance Techniques for Processors.- Proposed Techniques to Detect Transient Faults in Processors.- Simulation Fault Injection Experimental Results.- Configuration Bitstream Fault Injection Experimental Results.- Radiation Experimental Results.- Conclusions and Future Work.