Buch, Englisch, 172 Seiten, Format (B × H): 210 mm x 279 mm, Gewicht: 436 g
ISBN: 978-1-4684-8442-7
Verlag: Springer
presents a number of interesting strategies for designing and building high performance clock distribution networks. Many aspects of the ideas presented in these contributions are being developed and applied today in next-generation high-performance microprocessors.
Zielgruppe
Research
Autoren/Hrsg.
Weitere Infos & Material
Special Issue on High Performance Clock Distribution Networks Guest Editors’ Introduction.- Clock Skew Optimization for Peak Current Reduction.- Clocking Optimization and Distribution in Digital Systems with Scheduled Skews.- Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations.- Useful-Skew Clock Routing with Gate Sizing for Low Power Design.- Clock Distribution Methodology for PowerPCTM Microprocessors.- Circuit Placement, Chip Optimization, and Wire Routing for IBM IC Technology.- Practical Bounded-Skew Clock Routing.- A Clock Methodology for High-Performance Microprocessors.- Optical Clock Distribution in Electronic Systems.- Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits.




