VLSI Chip Design with the Hardware Description Language VERILOG

An Introduction Based on a Large RISC Processor Design
Erscheinungsjahr 2014
ISBN: 978-3-642-64650-8
Verlag: Springer

Buch, Englisch, 360 Seiten, Format (B × H): 155 mm x 235 mm, Gewicht: 569 g

The art of transforming a circuit idea into a chip has changed permanently. Formerly, the electrical, physical and geometrical tasks were predominant. Later, mainly net lists of gates had to be constructed. Nowadays, hardware description languages (HDL) similar to programming languages are central to digital circuit design. HDL-based design is the main subject of this book.
After emphasizing the economic importance of chip design as a key technology, the book deals with VLSI design (Very Large Scale Integration), the design of modern RISC processors, the hardware description language VERILOG, and typical modeling techniques. Numerous examples as well as a VERILOG training simulator are included on a disk.

Zielgruppe

Research

Autoren/Hrsg.

Golze, Ulrich

Weitere Mitwirkende

Blinzer, P.

Cochlovius, E.

Schäfers, M.

Wachsmann, K.-P.

Fachgebiete

• Mathematik | Informatik EDV | Informatik Informatik Rechnerarchitektur
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik

Inhaltsverzeichnis

Design of VLSI Circuits.- Design of VLSI Circuits.- RISC Architectures.- RISC Architectures.- Short Introduction to VERILOG.- Short Introduction to VERILOG.- External Specification of Behavior.- External Specification of Behavior.- Internal Specification of Coarse Structure.- Internal Specification of Coarse Structure.- Pipeline of the Coarse Structure Model.- Pipeline of the Coarse Structure Model.- Synthesis of Gate Model.- Synthesis of Gate Model.- Testing, Testability, Tester, and Testboard.- Testing, Testability, Tester, and Testboard.- Summary and Prospect.- Summary and Prospect.- HDL Models for Circuits and Architectures.- HDL Modeling with VERILOG.