Risc-V System-On-Chip Design

Erscheinungsjahr 2026
ISBN: 978-0-323-99498-9
Verlag: Elsevier Science

Buch, Englisch, 600 Seiten, Format (B × H): 191 mm x 235 mm, Gewicht: 450 g

RISC-V Microprocessor System-On-Chip Design is written to be accessible to an advanced undergraduate audience with limited background. It explains concepts from operating systems, VLSI, and memory systems as necessary, and High school mathematics is sufficient preparation for most of the book, although the floating point and division chapters will be primarily of interest to those with a curiosity about computer arithmetic. Like Harris and Harris’s Digital Design and Computer Architecture textbooks, this book will appeal to students with easy-to-read and complete explanations, sidebars, and occasional humor and cartoons.

It comes with an open-source implementation and will include end-of-chapter problems to extend the RISC-V processor in various ways. Ancillary materials include a GitHub repository with complete open-source SystemVerilog code, validation code in C and assembly language, and code for benchmarking and booting Linux.

Autoren/Hrsg.

Harris, David

Stine, James

Harris, Sarah

Thompson, Rose

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise
• Mathematik | Informatik EDV | Informatik Informatik Rechnerarchitektur

Inhaltsverzeichnis

Preface
How to Use This Book
Acknowledgements
About the Authors
Foreword

01. A Brief History of Computer Design

02. Introduction to RISC-V
03. RISC-V Software Tool Flow

04. HDL Design Practices

05. Design Verification

06. Logic Synthesis

07. Pipelined Core

08. Privileged Operations

09. Bus Interface

10. Caches

11. Memory Management Unit

12. Load/Store Unit

13. Instruction Fetch Unit

14. Extensions: C (Compressed)

15. Extensions: M (Multiply and Divide)

16. Extensions: F/D/Q/Zfh/Zfa (Floating-Point)

17. Extensions: A (Atomic)

18. Extensions: Zb* and Zk* (Bit Manipulation and Cryptography)
19. Other Extensions

20. Peripherals

21. Benchmarking

22. Linux

23. FPGA Implementation

Appendix A Wally Synopsis
Appendix B Hitchhiker’s Guide to Linux

Appendix C Version Control using Git

Appendix D Tcl Book of Armaments

Appendix E Floating-Point Implementation
Bibliography
Index

Über Autor(innen)

Harris, Sarah
Sarah L. Harris is an Assistant Professor of Engineering at Harvey Mudd College. She received her Ph.D. and M.S. in Electrical Engineering from Stanford University. Before attending Stanford, she received a B.S. in Electrical and Computer Engineering from Brigham Young University. Sarah has also worked with Hewlett-Packard, the San Diego Supercomputer Center, Nvidia, and Microsoft Research in Beijing.
Sarah loves teaching, exploring and developing new technologies, traveling, wind surfing, rock climbing, and playing the guitar. Her recent exploits include researching sketching interfaces for digital circuit design, acting as a science correspondent for a National Public Radio affiliate, and learning how to kite surf. She speaks four languages and looks forward to learning more in the near future.

Harris, David
David Harris is the Harvey S. Mudd Professor of Engineering Design at Harvey Mudd College. He received his Ph.D. in electrical engineering from Stanford University and his M.Eng. in electrical engineering and computer science from MIT. Before attending Stanford, he worked at Intel as a logic and circuit designer on the Itanium and Pentium II processors. Since then, he has consulted at Sun Microsystems, Hewlett-Packard, Broadcom, and other design companies. David holds more than a dozen patents and is the author of three other textbooks on chip design, as well as many Southern California hiking guidebooks. When he is not working, he enjoys hiking, flying, and making things with his three sons.

Stine, James
James Stine is the Edward Joullian Professor of Engineering at Oklahoma State University. His area of research is in computer arithmetic, memory architectures, and Electronic Design Automation (EDA) design flow. He is the author of numerous articles on optimization of architectures for use with computer arithmetic as well as interfacing to memory architectures. He is the author of three texts: Digital Datapath Computer Arithmetic with Verilog, Adder Architectures for VLSI Implementations and System on Chip Design Flow and Standard-Cell Library.