Buch, Englisch, 279 Seiten, Format (B × H): 148 mm x 210 mm, Gewicht: 419 g
Buch, Englisch, 279 Seiten, Format (B × H): 148 mm x 210 mm, Gewicht: 419 g
Reihe: Berichte aus der Elektrotechnik
ISBN: 978-3-8191-0937-9
Verlag: Shaker Verlag
This work addresses the reliability of SiC devices under electro-chemical and thermo-mechanical stress via high humidity high temperature reverse bias (H3TRB) and power cycling tests (PCTs). The H3TRB results show that SiC devices can achieve an excellent performance. Compared to Si IGBTs with similar ratings, SiC MOSFETs exhibit a four times larger characteristic lifetime, but with a wider failure distribution. A novel degradation mechanism was discovered involving oxidation in the edge termination region, leading to vertical cracks near chip edges. Regarding PCTs, the temperature estimation via the VSD(T) method requires device-specific setup parameters for accuracy and methodologies to determine these are proposed. Tests on discrete SiC MOSFETs reveal significant differences in power cycling capability. The Coffin-Manson fits indicate variations in both baseline cycles to failure (Nf) and the Coffin-Manson exponent. Furthermore, the lifetime at lower temperature swings is substantially underestimated by standard model fits, suggesting a change in the exponent below a certain threshold. The Results also suggest that thinner chips exhibit a larger Coffin-Manson exponent, resulting in a steeper lifetime curve. PCTs on power modules confirm a lower power cycling capability for SiC compared to Si devices. The data at temperature swings of 60 K and below are underestimated by models derived from swings of 80 K and above. This discrepancy increases at lower swings and can be modeled by an exponent shift below a threshold temperature. Since this depends on baseline temperature, which is not considered in current models, adjustments are necessary to improve accuracy for SiC devices.
