Formal Verification Testbenches

Using Patterns for Reusable and Repeatable VLSI Design Quality
Erscheinungsjahr 2027
ISBN: 978-0-443-42889-0
Verlag: Elsevier Science

Buch, Englisch, 500 Seiten, Format (B × H): 191 mm x 235 mm, Gewicht: 449 g

Formal Verification (FV) has become an essential technology in the verification of IP, core, or SOC design. The authors' previous book, “Formal Verification: An Essential Toolkit for Modern VLSI Design”, offered the definitive guide to design and validation, with advice to help working engineers integrate these techniques into their work. However, understanding the technology is only the beginning: to really use FV effectively, there are many practical considerations in creating effective testbenches. It’s important to use the right formal tools depending on the preferred design style, project phase, and verification goals. Formal Verification Testbenches: Using Patterns for Reusable and Repeatable VLSI Design Quality is designed to provide that guidance, to assist the transition from initial FV usage to FV being the main workhorse of the validation flow. In addition to describing general principles of FV testbench development that apply to any design style, the book takes a deep dive into real testbenches for specific examples: arbiters, sequence controllers, memory controllers, fsm-heavy control blocks, clock gating designs, and dot-product accumulate blocks. It also highlights new opportunities within the field, for example using AI to plan and execute FV. Formal Verification Testbenches: Using Patterns for Reusable and Repeatable VLSI Design Quality enables a design team to confidently plan and execute a project whose primary validation method will be formal verification.

Autoren/Hrsg.

Kumar, M .V. Achutha Kiran

Jain, Anshul

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik
• Geisteswissenschaften Architektur Architektur: Allgemeines
• Mathematik | Informatik EDV | Informatik Technische Informatik Computersicherheit
• Mathematik | Informatik EDV | Informatik Informatik Rechnerarchitektur
• Technische Wissenschaften Bauingenieurwesen Bauingenieurwesen
• Wirtschaftswissenschaften Wirtschaftssektoren & Branchen Fertigungsindustrie

Inhaltsverzeichnis

1. Formal Testbench: Overview
2. Using Basic GenAI (GenFV)
3. Architecture formal
4. Practical Compliance Monitor: Assertion based VIP
5. First Practical FPV Testbench: Arbiters
6. Second Practical FPV Test bench: Sequence Controllers
7. Third Practical FV Testbench: Inter-related FSMs
8. Fourth Practical FPV TB: Memory Controller
9. Fifth Practical FEV TB: Clock gating Design
10. Sixth Practical FV TB: CvsRTL on Dot Product Accumulate Design
11. Seventh Practical FV TB: Post Silicon Bug Reproduction
12. Best Practices and Pitfalls
13. The Future of Formal Verification*
14. Conclusion
15. Appendix

Über Autor(innen)

Kumar, M .V. Achutha Kiran
M V Achutha Kiran Kumar is an Intel Fellow in the Design Engineering group at intel and leads the company’s Formal Verification Central Technology Office, one of the largest industrial Formal Verification teams in the world. He has over 19 years experience where he worked in various areas of the chip design cycle which includes RTL design, structural design, circuit design, simulation and various levels of validation including formal verification. He is the co-author of 'Formal Verification - An Essential toolkit for the Hardware Design'.

Jain, Anshul
Anshul Jain is the Principal Engineer at Intel’s Formal Verification Central Technology Office, and formerly a Formal Verification consultant at Oski Technologies.