Electronic Design Automation for Integrated Circuits Handbook, Two Volume Set, Third Edition

3. Auflage 2026
ISBN: 978-1-032-93574-4
Verlag: Taylor & Francis

Buch, Englisch, 1500 Seiten, Format (B × H): 210 mm x 280 mm, Gewicht: 2960 g

Comprised of two volumes, Electronic Design Automation for Integrated Circuits Handbook, Third Edition addresses all major areas of EDA for integrated circuits (ICs). Chapters contributed by leading experts authoritatively discuss an array of topics ranging from system design to physical implementation.

New to This Edition:

· Major updates appearing in the initial phases of the design flow, where the level of abstraction keeps rising to support more functionality with lower non-recurring engineering (NRE) costs

· Significant revisions reflected in the final phases of the design flow, where the complexity due to smaller and smaller geometries is compounded by the slow progress of shorter wavelength lithography

· New coverage of cutting-edge applications and approaches realized in the decade since the publication of the second edition—these are illustrated by updates including the impact of AI/ML and new analog layout methods, new high-level synthesis algorithms, and power-optimized design

Offering improved depth and modernity, Electronic Design Automation for Integrated Circuits Handbook, Third Edition – Two-Volume Set provides a valuable, state-of-the-art reference for EDA students, researchers, and professionals.

Zielgruppe

General

Autoren/Hrsg.

Lavagno, Luciano

Martin, Grant E.

Markov, Igor L.

Scheffer, Louis K.

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Halb- und Supraleitertechnologie
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise

Inhaltsverzeichnis

Volume I: Electronic Design Automation for IC System Design, Verification, and Testing

Volume II: Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology

Über Autor(innen)

Luciano Lavagno received his Ph.D. in EECS from U.C. Berkeley in 1992 and from Politecnico di Torino in 1993. He co-authored two books on asynchronous circuit design, a book on hardware/software co-design of embedded systems, and over 250 scientific papers. Between 1993 and 2000 he was the architect of the POLIS project, a cooperation between U.C. Berkeley, Cadence Design Systems, Magneti Marelli and Politecnico di Torino, which developed a complete hardware/software co-design environment for control-dominated embedded systems. Between 2003 and 2014 he was one of the creators and architects of the Cadence CtoSilicon high-level synthesis system. Since 2011, Dr. Lavagno has been a full professor with Politecnico di Torino, Italy. He has served on the technical committees of several international conferences in his field (e.g. DAC, DATE, ICCAD, ICCD, ASYNC, CODES) as well as various workshops and symposia and is a senior member of IEEE. He has also been an associate editor of IEEE TCAS and ACM TECS. His research interests include the high-level synthesis of digital circuits and the acceleration of Machine learning algorithms using Field Programmable Gate Arrays.

Grant E. Martin retired from his position as a distinguished engineer at Cadence Design Systems, Inc., San Jose, California, USA, in 2023. Before that, Grant worked for Burroughs in Scotland for 6 years; Nortel/Bell-Northern Research in Canada for 10 years; Cadence Design Systems for 9 years, eventually becoming a fellow in their labs; and Tensilica for 9 years. He rejoined Cadence in 2013 when it acquired Tensilica, and has been there since, working in the Tensilica part of the Cadence Intellectual Property Group. He received his bachelor’s and master’s degrees in mathematics (combinatorics and optimization) from the University of Waterloo, Ontario, Canada, in 1977 and 1978. Grant has coauthored and coedited several books, including the first-ever book on system-on-chip (SoC) design published in Russian. He has also presented many papers, talks, and tutorials, and participated in panels at several major conferences. He cochaired the VSI Alliance Embedded Systems Study Group in the summer of 2001 and was co-chair of the Design Automation Conference Technical Program Committee for Methods for 2005 and 2006. He is a senior member of IEEE. Although retired, he continues to have an interest in system-level design, IP-based design of system-on-chip, platform-based design, DSP, baseband and image processing, and embedded software.