Source-Synchronous Networks-On-Chip

Circuit and Architectural Interconnect Modeling
Softcover Nachdruck of the original 1. Auflage 2014
ISBN: 978-1-4939-4817-8
Verlag: Springer

Buch, Englisch, 143 Seiten, Previously published in hardcover, Format (B × H): 155 mm x 235 mm, Gewicht: 2526 g

This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.

Zielgruppe

Research

Autoren/Hrsg.

Mandal, Ayan

Mahapatra, Rabi

Khatri, Sunil P.

Fachgebiete

• Mathematik | Informatik EDV | Informatik Technische Informatik Eingebettete Systeme
• Mathematik | Informatik EDV | Informatik Computerkommunikation & -vernetzung
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Mikroprozessoren

Inhaltsverzeichnis

Introduction.- Clock Distribution for fast Networks-on-Chip.- Fast Network-on-Chip Design.- Fast On-Chip Data transfer using Sinusoid Signals.- Conclusion and Future Work.