Manufacturability Aware Routing in Nanometer VLSI

1. Auflage 2010
ISBN: 978-1-60198-350-3
Verlag: Now Publishers

Buch, Englisch, Band 11, 100 Seiten, Format (B × H): 156 mm x 234 mm

Reihe: Foundations and Trends® in Electronic Design Automation

This paper surveys key research challenges and recent results of manufacturability aware routing in nanometer VLSI designs. The manufacturing challenges have their root causes from various integrated circuit (IC) manufacturing processes and steps, e.g., deep sub-wavelength lithography, random defects, via voids, chemical-mechanical polishing, and antenna-effects. They may result in both functional and parametric yield losses. The manufacturability aware routing can be performed at different routing stages including global routing, track routing, and detail routing, guided by both manufacturing process models and manufacturing-friendly rules. The manufacturability/yield optimization can be performed through both correct-by-construction (i.e., optimization during routing) as well as construct-by-correction (i.e., post-routing optimization). This paper will provide a holistic view of key design for manufacturability issues in nanometer VLSI routing.

Autoren/Hrsg.

Pan, David Z.

Cho, Minsik

Yuan, Kun

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Schaltungsentwurf

Inhaltsverzeichnis

1: Introduction 2: CMP Aware Routing 3: Random-Defect Aware Routing 4: Lithography Aware Routing 5: Redundant Via Aware Routing 6: Antenna-Effect Aware Routing 7: Other DFM Issues in VLSI Routing 8: Conclusions. References