The Dark Side of Silicon

Energy Efficient Computing in the Dark Silicon Era
1. Auflage 2017
ISBN: 978-3-319-31594-2
Verlag: Springer

Buch, Englisch, 347 Seiten, Format (B × H): 160 mm x 241 mm, Gewicht: 6565 g

This book presents the state-of-the art of one of the main concerns with microprocessors today, a phenomenon known as "dark silicon".  Readers will learn how power constraints (both leakage and dynamic power) limit the extent to which large portions of a chip can be powered up at a given time, i.e. how much actual performance and functionality the microprocessor can provide. The authors describe their research toward the future of microprocessor development in the dark silicon era, covering a variety of important aspects of dark silicon-aware architectures including design, management, reliability, and test.  Readers will benefit from specific recommendations for mitigating the dark silicon phenomenon, including energy-efficient, dedicated solutions and technologies to maximize the utilization and reliability of microprocessors.   

Zielgruppe

Professional/practitioner

Autoren/Hrsg.

Rahmani, Amir M.

Liljeberg, Pasi

Hemani, Ahmed

Jantsch, Axel

Tenhunen, Hannu

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Mikroprozessoren
• Technische Wissenschaften Energietechnik | Elektrotechnik Energieeffizienz
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise
• Technische Wissenschaften Technik Allgemein Nachhaltigkeit, Grüne Technologien

Inhaltsverzeichnis

Introduction.- Dark vs. Dim Silicon and Near-Threshold Computing.- The SiLago Solution: Architecture and Design Methods for a Heterogeneous Dark Silicon aware Coarse Grain Reconfigurable Fabric.- Heterogeneous Dark Silicon Chip Multi-Processors Design and Run-time Management.- Thermal Safe Power (TSP) - Efficient Thermal-Aware Power Budgeting for Manycore Systems in Dark Silicon.- Power Management of Asymmetric Multi-Cores in the Dark Silicon Era.- Multi-Objective Power Management for CMPs in the Dark Silicon Age.- Robust Application Scheduling with Adaptive Parallelism in Dark-Silicon Constrained Multicore Systems.- Dark Silicon Patterning: Ef?cient Power Utilization through Run-time Mapping.- Online Software-Based Self-Testing in the Dark Silicon Era.- Adroit Use of Dark Silicon for Power, Performance and Reliability Optimization of NoCs.- NoC-aware Computational Sprinting.-

Über Autor(innen)

Prof. Dr.h.c Prof.h.c. Hannu Tenhunen is chair professor of Electronic Systems at Royal Institute of Technology (KTH), Stockholm, Sweden. Prof. Tenhunen has held professor position as full professor, invited professor or visiting honorary professor in Finland (TUT, UTU), Sweden (KTH), USA (Cornel U), France (INPG), China (Fudan and Beijing Jiatong Universities), and Hong Kong (Chinese University of Hong Kong), and has an honorary doctorate from Tallinn Technical University.

He has been director of multiple national large scale research programs or being an initiator and director of national or European graduate schools. He has actively contributed on VLSI and SoC design in Finland and Sweden via creating new educational programs and research directions, most lately at European level as being the EU-level Education Director of the new European flagship initiative European Institute of Technology and Innovations (EIT), and its Knowledge and Innovation Community EIT ICT Labs. Prof. Tenhunen has been active in promoting the innovation system and innovation support mechanism in research and education both at national and European level.

Prof. Tenhunen has been a board member in science parks, start-up companies, and has served as advisor or expert for high technology companies and venture capitalists, as well as evaluator for EU and national programs and research institutes. He has supervised over 70 M.Sc. thesis, 39 doctoral thesis, and 8 post-doc. From his doctoral students and post-docs, as of today, 21 are currently professors and associate professors.