Low Power and Process Variation Aware Sram and Cache Design

1. Auflage 2015
ISBN: 978-1-4614-2271-6
Verlag: Springer

Buch, Englisch, 200 Seiten, Format (B × H): 155 mm x 235 mm

This book addresses process variability and power management for embedded memories, which are becoming dominant components in today’s Systems on Chip (SoCs). It provides thorough background on voltage scaling and the reliability effects on memories, while describing memory behavior at different voltages and frequencies. The authors describe a cross-layer approach, simultaneously targeting the manufacturing of devices, the inner-design of the memory circuits, as well as the way they are architected into a system. This approach enables the design of reliable, power-efficient systems in which memories are dominating area, power, and performance.

Zielgruppe

Research

Autoren/Hrsg.

Sasan, Avesta

Kurdahi, Fadi

Eltawil, Ahmed

Fachgebiete

• Mathematik | Informatik EDV | Informatik Technische Informatik Eingebettete Systeme
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Halb- und Supraleitertechnologie
• Mathematik | Informatik EDV | Informatik Technische Informatik Hardware: Grundlagen und Allgemeines

Inhaltsverzeichnis

Introduction.- SCPS Cache.- RDC-Cache.- IDC-Cache.- VTD-Cache.- Conclusions.