Low Power Networks-on-Chip

2011
ISBN: 978-1-4899-9437-0
Verlag: Springer US

Buch, Englisch, 287 Seiten, Previously published in hardcover, Format (B × H): 155 mm x 235 mm, Gewicht: 470 g

In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.

Zielgruppe

Research

Autoren/Hrsg.

Silvano, Cristina

Palermo, Gianluca

Lajolo, Marcello

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise
• Mathematik | Informatik EDV | Informatik Professionelle Anwendung Computer-Aided Design (CAD)

Inhaltsverzeichnis

Network-on-Chip Power Estimation.- Timing.- synchronous/asynchronous communication.- Network-on-Chip link design.- Topology exploration.- Network-on-Chip support for CMP/MPSoCs.- Network design for 3D stacked logic and memory.- Beyond the wired Network-on-Chip.