Wang / Ledley | Comp Arch Security C | Buch | 978-1-118-16881-3 | www.sack.de

Buch, Englisch, 360 Seiten, Format (B × H): 172 mm x 251 mm, Gewicht: 672 g

Wang / Ledley

Comp Arch Security C


1. Auflage 2012
ISBN: 978-1-118-16881-3
Verlag: John Wiley & Sons

Buch, Englisch, 360 Seiten, Format (B × H): 172 mm x 251 mm, Gewicht: 672 g

ISBN: 978-1-118-16881-3
Verlag: John Wiley & Sons


The first book to introduce computer architecture for security and provide the tools to implement secure computer systems

This book provides the fundamentals of computer architecture for security. It covers a wide range of computer hardware, system software and data concepts from a security perspective. It is essential for computer science and security professionals to understand both hardware and software security solutions to survive in the workplace.
- Examination of memory, CPU architecture and system implementation
- Discussion of computer buses and a dual-port bus interface
- Examples cover a board spectrum of hardware and software systems
- Design and implementation of a patent-pending secure computer system
- Includes the latest patent-pending technologies in architecture security
- Placement of computers in a security fulfilled network environment
- Co-authored by the inventor of the modern Computed Tomography (CT) scanner
- Provides website for lecture notes, security tools and latest updates

Wang / Ledley Comp Arch Security C jetzt bestellen!

Weitere Infos & Material


About the Authors xv

Preface xvii

Acknowledgements xix

1 Introduction to Computer Architecture and Security 1

1.1 History of Computer Systems 3

1.2 John von Neumann Computer Architecture 34

1.3 Memory and Storage 36

1.4 Input/Output and Network Interface 37

1.5 Single CPU and Multiple CPU Systems 38

1.6 Overview of Computer Security 41

1.7 Security Problems in Neumann Architecture 46

1.8 Summary 48

Exercises 48

References 50

2 Digital Logic Design 51

2.1 Concept of Logic Unit 51

2.2 Logic Functions and Truth Tables 52

2.3 Boolean Algebra 54

2.4 Logic Circuit Design Process 55

2.5 Gates and Flip-Flops 56

2.6 Hardware Security 58

2.7 FPGA and VLSI 58

2.8 Summary 65

Exercises 67

References 67

3 Computer Memory and Storage 68

3.1 A One Bit Memory Circuit 68

3.2 Register, MAR, MDR and Main Memory 70

3.3 Cache Memory 72

3.4 Virtual Memory 74

3.5 Non-Volatile Memory 76

3.6 External Memory 77

3.7 Memory Access Security 86

3.8 Summary 88

Exercises 89

References 89

4 Bus and Interconnection 90

4.1 System Bus 90

4.2 Parallel Bus and Serial Bus 95

4.3 Synchronous Bus and Asynchronous Bus 107

4.4 Single Bus and Multiple Buses 109

4.5 Interconnection Buses 110

4.6 Security Considerations for Computer Buses 111

4.7 A Dual-Bus Interface Design 112

4.8 Summary 115

Exercises 117

References 117

5 I/O and Network Interface 118

5.1 Direct Memory Access 118

5.2 Interrupts 120

5.3 Programmed I/O 121

5.4 USB and IEEE 1394 122

5.5 Network Interface Card 136

5.6 Keyboard, Video and Mouse (KVM) Interfaces 139

5.7 Input/Output Security 140

5.8 Summary 141

Exercises 142

References 143

6 Central Processing Unit 144

6.1 The Instruction Set 144

6.2 Registers 153

6.3 The Program Counter and Flow Control 158

6.4 RISC Processors 161

6.5 Pipelining 164

6.6 CPU Security 166

6.7 Virtual CPU 168

6.8 Summary 169

Exercises 170

References 170

7 Advanced Computer Architecture 172

7.1 Multiprocessors 172

7.2 Parallel Processing 177

7.3 Ubiquitous Computing 182

7.4 Grid, Distributed and Cloud Computing 187

7.5 Internet Computing 197

7.6 Virtualization 203

7.7 Biocomputers 209

7.8 Summary 211

Exercises 212

References 214

8 Assembly Language and Operating Systems 216

8.1 Assembly Language Basics 217

8.2 Operation Code and Operands 223

8.3 Direct Addressing 225

8.4 Indirect Addressing 225

8.5 Stack and Buffer Overflow 226

8.6 FIFO and M/M/1 Problem 232

8.7 Kernel, Drivers and OS Security 234

8.8 Summary 238

Exercises 239

References 240

9 TCP/IP and Internet 241

9.1 Data Communications 241

9.2 TCP/IP Protocol 244

9.3 Network Switches 248

9.4 Routers 250

9.5 Gateways 257

9.6 Wireless Networks and Network Address Translation (NAT) 258

9.7 Network Security 267

9.8 Summary 275

Exercises 276

9.9 Virtual Cyber-Security Laboratory 277

References 278

10 Design and Implementation: Modifying Neumann Architecture 280

10.1 Data Security in Computer Systems 280

10.2 Single-Bus View of Neumann Architecture 284

10.3 A Dual-Bus Solution 286

10.4 Bus Controller 288

10.5 Dual-Port Storage 292

10.6 Micro-Operating System 292

10.7 Summary 293

Exercises 294

10.8 Projects 295

References 295

Appendix A Digital Logic Simulators 297

A.1 CEDAR Logic Simulator 297

A.2 Logisim 298

A.3 Digital Logic Simulator v0.4 298

A.4 Logicly 299

Appendix B Computer Security Tools 300

B.1 Wireshark (Ethereal) 300

B.2 Metasploit 300

B.3 Nessus 301

B.4 Aircrack 301

B.5 Snort 301

B.6 Cain and Abel 302

B.7 BackTrack 302

B.8 Netcat 302

B.9 Tcpdump 302

B.10 John the Ripper 303

Appendix C Patent Application: Intrusion-Free Computer Architecture for Information and Data Security 304

C.1 Background of the Invention 304

C.1.1 John von Neumann Computer Architecture Model 305

C.1.2 Modified Neumann Computer Architecture 305

C.1.3 Problems Existed in the John Neumann Model 307

C.1.4 The Goal of the Invention 307

C.2 Field of Invention 308

C.3 Detailed Description of the Invention 308

C.4 Claim 310

Index 313


Shuangbao (Paul) Wang, George Mason University, USA

Robert S. Ledley, Georgetown University, USA



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