Agnew / Claesen / Camposano Computer Hardware Description Languages and their Applications

Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications - CHDL '93 Sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC, Ottawa, Ontario, Canada, 26-28 April, 1993
1. Auflage 2014
ISBN: 978-1-4832-9802-3
Verlag: Elsevier Science & Techn.
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, Band Volume 32, 618 Seiten, Web PDF

Reihe: IFIP Transactions A: Computer Science and Technology

Hardware description languages (HDLs) have established themselves as one of the principal means of designing electronic systems. The interest in and usage of HDLs continues to spread rapidly, driven by the increasing complexity of systems, the growth of HDL-driven synthesis, the research on formal design methods and many other related advances.This research-oriented publication aims to make a strong contribution to further developments in the field. The following topics are explored in depth: BDD-based system design and analysis; system level formal verification; formal reasoning on hardware; languages for protocol specification; VHDL; HDL-based design methods; high level synthesis; and text/graphical HDLs. There are short papers covering advanced design capture and recent work in high level synthesis and formal verification. In addition, several invited presentations on key issues discuss and summarize recent advances in real time system design, automatic verification of sequential circuits and languages for protocol specification.

Autoren/Hrsg.

Agnew, D.

Claesen, L.

Camposano, R.

Inhaltsverzeichnis

1;Front Cover;1
2;Computer Hardware Description Languages and Their Applications;4
3;Copyright Page;5
4;Table of Contents;15
5;Preface;6
6;Conference Organization;8
7;"Real Time Distributed Systems (invited presentation)" Mario R. Barbacci, Carnegie Mellon University;16
8;Real-time Distributed Systems;18
8.1;1. Introduction;18
8.2;2. Industrial Computing Applications;18
8.3;3. The Real-Time Distributed Systems Program at the SEI;19
8.4;4. A Science and Technology Maturity Model;23
8.5;5. An Industrial Computing Developers Handbook;24
9;Session : BDD-based Design and Analysis Techniques chair: Luc Claesen;28
10;Verification of the Futurebus+ Cache Coherence Protocol*;30
10.1;1. INTRODUCTION;31
10.2;2. TEMPORAL LOGIC MODEL CHECKING;32
10.3;3. SMV;34
10.4;4. OVERVIEW OF THE PROTOCOL;37
10.5;5. MODELING THE PROTOCOL;39
10.6;6. SPECIFYING CACHE COHERENCE;40
10.7;7. SOME ERRORS FOUND DURING VERIFICATION;42
10.8;8. CONCLUSIONS;44
10.9;9. ACKNOWLEDGMENTS;45
10.10;10. REFERENCES;45
11;Chapter 03."Exploiting Symbolic Traversal Techniques for Efficient Process Algebra Manipulation";46
11.1;1 Introduction;46
11.2;2 The rationale of Process Algebras;47
11.3;3 Symbolic Traversal Techniques;50
11.4;4 Symbolic Generation of Process Algebra Agents;51
11.5;5 Experimental Results;55
11.6;6 Conclusions;56
11.7;References;57
12;Chapter 04."Hardware- Verification using First Order BDDs ";60
12.1;1 Introduction;60
12.2;2 First Order BDD-like Calculi;61
12.3;3 A Hierarchical Hardware Case Study;71
12.4;4 Experimental Results;75
12.5;5 Summary;76
12.6;References;77
13;Session: HDL-based Design Methods chair: Franz Rammig;78
14;Chapter 05."HW/SW Co-Design with PRAMs Using CoDES";80
14.1;1. Introduction;80
14.2;2. Parallel Random Access Machines;81
14.3;3. System Overview;83
14.4;4. Principal Design Steps;84
14.5;5. Example;89
14.6;6. Conclusion and Future Work;91
14.7;7. References;92
15;Chapter 06."Prevail-DM: A Framework-Based Environment for Formal Hardware Verification ";94
15.1;1 INTRODUCTION;94
15.2;2 INTRODUCTION TO PREVAIL;96
15.3;3 OVERVIEW OF PREVAIL-DM;96
15.4;4 CONCEPTUAL SCHEMA;98
15.5;5 IMPLEMENTATION ASPECTS;105
15.6;6 ANALYSIS OF THE ENVIRONMENT;106
15.7;7 DESIGN METHODOLOGY MANAGEMENT;107
15.8;8 FINAL REMARKS;109
15.9;Acknowledgments;110
15.10;References;110
16;Chapter 07."Better Verification Through Symmetry";112
16.1;1 Introduction;112
16.2;2 Symmetry and the Murf Verification System;113
16.3;3 Better Verification;119
16.4;4 Practical Results;123
16.5;5 Data saturation;124
16.6;6 Conclusion;125
16.7;Acknowledgements;125
16.8;References;126
17;Session: Synthesis and Verification chair: Mario Barbacci;128
18;Chapter 08."A Rewriting Based Method for the Formal Verification of Microprocessors";130
18.1;1 Introduction;130
18.2;2 Overview of the problem;131
18.3;3 Implementation of this method;133
18.4;4 Applications;135
18.5;5 Conclusion;136
18.6;References;136
19;Chapter 09."Reasoning about the VHDL Standard Logic Package Signal Data Type ";138
19.1;1 Motivation;138
19.2;2 Modeling Signal Values;139
19.3;3 Example;142
19.4;4 Conclusion;144
19.5;5 Acknowledgements;144
19.6;References;145
20;Chapter 10."An Efficient Data-Path Synthesis Based on Algorithmic Description under the Constraints of Time and Area";146
20.1;1. INTRODUCTION;146
20.2;2. FINDING REDESIGNING METHODS;147
20.3;3. REDESIGN;149
20.4;4. EXPERIMENTS;151
20.5;5. CONCLUDING REMARKS;152
20.6;6. REFERENCES;153
21;Chapter 11."Integrating Boolean Verification with Formal Derivation";154
21.1;1. Introduction;154
21.2;2. DDD - D_igital D_esign D_erivation System;155
21.3;3. The DDD-FM9001 Project;157
21.4;4. Verification of the DDD-FM9001 ALU;158
21.5;5. Concluding Remarks;160
21.6;REFERENCES;160
22;Chapter 12."Automated High-level Verification Against Clocked Algorithmic Specifications";162
22.1;1 Introduction;162
22.2;2 Representation;163
22.3;3 Algorithm;164
22.4;4 Experimental results and future work;166
22.5;References;166
23;Chapter 13."The Backward Walk Approach in FSM Verification";170
23.1;1 Introduction;170
23.2;2 Notations and Definitions;171
23.3;3 Our Algorithm;172
23.4;4 Hopcroft's Algorithm;173
23.5;5 Data Structure of the Partition;173
23.6;6 Filkorn's Method;174
23.7;7 The Detection of Non-reachable States;174
23.8;8 Experiments;175
23.9;9 Conclusion and Future Work;176
23.10;Acknowledgments;177
23.11;References;177
24;Invited Presentation : Automatic Verification of Sequential Circuit Designs Edmund M. Clarke, Carnegie Mellon University;178
25;Automatic Verification of Sequential Circuit Designs;180
26;Session: Protocol Specification chair: Ed Cerny;182
27;Chapter 14."Toward a Basis for Protocol Specification and Process Decomposition ";184
27.1;1. Introduction;184
27.2;2. A Language for Protocol Specification;186
27.3;4. Interpretation;190
27.4;5. Relations

and Operations on Machines;193
27.5;6. An Example of Process Decomposition;197
27.6;7. Observations and Conclusion;199
27.7;8. Acknowledgements;199
27.8;REFERENCES;200
28;Chapter 15."Integrating SDL and VHDL for System-Level Hardware Design";202
28.1;1 Introduction;202
28.2;2 WHAT IS SDL ?;204
28.3;3 SDL and Object-Oriented Design of Hardware;205
28.4;4 An SDL-Based Hardware Design Environment;208
28.5;5 Example;212
28.6;6 Conclusions;216
28.7;Acknowledgement;217
28.8;References;217
29;Session:Formal Reasoning about Regular Structures

chair: Carlos Delgado Kloos;220
30;Chapter 16. Reasoning About Array Structures Using a Dependently Typed Logic
;222
30.1;1 Introduction;222
30.2;2 The Veritas Design Logic;224
30.3;3 Array Structures;227
30.4;4 Systolic Arrays;233
30.5;5 Triangular Dependency Graph Example;236
30.6;6 Conclusions;238
30.7;7 Acknowledgements;239
30.8;References;239
31;Chapter 17."VHDL Description and Formal Verification of Systolic Multipliers";240
31.1;I. INTRODUCTION;240
31.2;II. ILLUSTRATIVE EXAMPLE.;241
31.3;III. OVERVIEW OF THE BOYER-MOORE SYSTEM.;243
31.4;IV. MODELLING SYSTOLIC MULTIPLIERS WITH BOYER-MOORE.;244
31.5;V. PROOF METHODOLOGY.;248
31.6;VI. GENERALIZING THE SPECIFICATION.;250
31.7;VII. A MORE COMPLEX EXAMPLE.;253
31.8;VIII . CONCLUSION.;256
31.9;ACKNOWLEDGEMENTS;257
31.10;REFERENCES;257
32;Chapter 18.Transformational Rewriting with Ruby;258
32.1;1. Introduction;258
32.2;2 .The Ruby Language;259
32.3;3· Rewriting Ruby Terms;262
32.4;4. The Rewrite Process;267
32.5;5. Conclusion;274
32.6;6. Acknowledgements;274
32.7;References;274
33;Session: High Level Synthesis chair: Flavio Wagner;276
34;Chapter 19."A Representation for the Binding of RT-Component Functionality to HDL Behavior";278
34.1;1. Introduction;278
34.2;2. Related Work;281
34.3;3. Representation of Component Functions and Bindings;282
34.4;4. Example Application;288
34.5;5. Further Examples;292
34.6;6. Summary and Future Directions;293
34.7;Acknowledgments;294
34.8;References;294
35;Chapter 20."Performance Specification and Measurement";296
35.1;1 Introduction;296
35.2;2 An Invitation to PDL;298
35.3;3 PDL: The Language;300
35.4;4 Advanced features;304
35.5;5 Dynamic Attributes;307
35.6;6 Compiling PDL;309
35.7;7 PDL - VHDL translation;310
35.8;8 PDL: Execution Environment;311
35.9;9 Results and Future Work;311
35.10;10 Acknowledgements;312
35.11;References;312
36;Chapter 21."Automatic Synthesis of Sequential Synchronizations";314
36.1;1 Introduction;314
36.2;2 The Specification Language
;316
36.3;3 Specification of Digital Components;322
36.4;4 Synchronization Specification and Derivation;324
36.5;5 Solving Systems of Inequalities;325
36.6;6 Conclusion;329
36.7;References;329
37;Session:Design Capture chair: Edmund M. Clarke;332
38;Chapter 22."Specifying Hardware Systems in LOTOS";334
38.1;1. Introduction and Background;334
38.2;2.Formal Specifications of Small Digital Circuits;335
38.3;3. Validating the Specification;339
38.4;4. Conclusions and Research Directions;340
38.5;References;340
39;Chapter 23."HML: A Hardware Description Language Based on Standard ML";342
39.1;1 Introduction;342
39.2;2 The HML Language;344
39.3;3 An Example : A Floating Point Adder;347
39.4;4 Conclusion;348
39.5;Acknowledgements;349
39.6;References;349
40;Chapter 24."An Efficient Object-Oriented Variation of the Statecharts Formalism for Distributed Real-Time Systems";350
40.1;1. INTRODUCTION;350
40.2;2. AN OVERVIEW OF ROOM;351
40.3;3. ROOMCHARTS;352
40.4;4. INHERITANCE;357
40.5;5. RELATED WORK;357
40.6;6. EXPERIENCE WITH ROOMCHARTS;358
40.7;Acknowledgments;359
40.8;7. REFERENCES;359
41;Chapter 25."Linking System Design Tools and Hardware Design Tools
;360
41.1;1. Introduction;360
41.2;2. Previous Work;361
41.3;3. COSMOS: Linking The Worlds Of System Design And Circuit Design;362
41.4;4. Conclusions And Future Work;365
41.5;References;366
42;Chapter 26."Automatic VHDL Model Generation System";14
43;Chapter 27.Automatic VHDL Model Generation System;368
43.1;1. INTRODUCTION;368
43.2;2. AUTOMATIC VHDL MODEL GENERATION;369
43.3;3. PREPROCESSOR AND POSTPROCESSOR;370
43.4;4. AUTOMATIC CODE GENERATOR;371
43.5;5. AUTOMATIC MODEL CHECKER;373
43.6;6. MODEL LIBRARY AND RULE BASE;374
43.7;7. RESULTS;374
43.8;8. CONCLUSION;374
43.9;9. REFERENCES;375
44;Chapter 28."The Modeler's Assistant: A CAD Tool for Behavioral Model Development";376
44.1;1. THE PROCESS MODEL GRAPH REPRESENTATION;376
44.2;2. THE MODELERS ASSISTANT;378
44.3;3. REFERENCES;383
45;Chapter 29."Insulin: An Instruction Set Simulation Environment";384
45.1;1. Introduction;384
45.2;2. The Micro-Architecture Design System;385
45.3;3. Instruction Set Simulation;386
45.4;4. Comparison with Existing Systems;390
45.5;5. Conclusion;390
45.6;6. References;391
46;"Specification languages for communication protocols (invited presentation)";392
47;Session: Timing Specifications in HDLs chair: John Brzozowski;412
48;Chapter 30."Integrating Behavior and Timing in Executable Specifications";414
48.1;1 Introduction;414
48.2;2 Interface Specifications;416
48.3;3 The Timing Diagram Interpreter;421
48.4;4 Procedural linking;423
48.5;5 A Complete Approach to Modeling;425
48.6;6 Discussion;429
48.7;7 Conclusion;430
48.8;References;431
49;Chapter 31."ESP: An Executable Specification Language for Mixed Timing Control Circuits ";432
49.1;1 Introduction;432
49.2;2 Background, Features and Basic Notions;434
49.3;3 Semantics of ESP Syntactic Constructs;438
49.4;4 Simulation of ESP using Simulation State Graphs;443
49.5;5 Partial Specification of the ISA Bus;445
49.6;6 Conclusion and Plans for Further Research;447
49.7;References;448
50;Session:Textual and Graphical HDLs chair: Robert Hum;450
51;Chapter 32."UDL/I version Two: A New Horizon of HDL Standards";452
51.1;1. Introduction;452
51.2;2. Requirements for the Standard HDLs;454
51.3;3. Design Philosophy of UDL/I Version Two;456
51.4;4. Features of UDL/I;457
51.5;5. Description example;462
51.6;6. UDL/I Committee Current Status and the Future Plan;464
51.7;7. Summary;466
51.8;Acknowledgments;466
51.9;References;467
52;Chapter 33."Verilog HDL Modeling Styles for Formal Verification";468
52.1;1 INTRODUCTION;469
52.2;2 NON-DETERMINISM IN THE VERILOG HDL;469
52.3;3 FINITE STATE MACHINE MODELING STYLES;470
52.4;4 SELECTION/RESOLUTION MODEL AND L-PROCESSES;471
52.5;5 GENERAL MODELING STYLE;474
52.6;6 DETERMINISTIC OUTPUT;476
52.7;7 DETERMINISTIC TRANSITIONS;477
52.8;8 TIMING EXTENSIONS;478
52.9;9 CONCLUSION;480
52.10;10 REFERENCES;480
53;Chapter 34."A Visual Hardware Description Language ";482
53.1;1 INTRODUCTION;482
53.2;2 RELATED WORK;483
53.3;3 A VISUAL APPROACH TO HARDWARE DES CRIPTION;484
53.4;4 A VISUAL SYNTAX FOR VHDL;487
53.5;5 DISCUSSION;494
53.6;Acknowledgements;496
53.7;References;496
54;Chapter 35."Textual/Graphical Design Concept-Level Synthesis";500
54.1;INTRODUCTION;500
54.2;CONCEPTUAL GRAPHS;501
54.3;BLOCK DIAGRAMS;504
54.4;TIMING DIAGRAMS;505
54.5;STATE TRANSITION DIAGRAMS;507
54.6;NATURAL LANGUAGE;508
54.7;INTEGRATION AND CONSISTENCY CHECKING;511
54.8;SYNTHESIS;515
54.9;CONCLUSIONS;516
54.10;REFERENCES;517
55;Sessions : VHDL;518
56;Chapter 36."System-Level Specification and Design Using VHDL: A Case Study";520
56.1;1 Introduction;520
56.2;2 The Causal Level;521
56.3;3 Specification and Design of the Processor at the Causal Level;522
56.4;4 Optimization Strategies;527
56.5;5 RT-level Optimizations of the Design Example;530
56.6;6 HW/SW Co - Specification and Co-Design;531
56.7;7 Analysis of the Design Example;533
56.8;8 Conclusion;535
56.9;Acknowledgements;535
56.10;References;535
57;Chapter 37."A Denotational Definition of the VHDL Simulation Kernel";538
57.1;1. Introduction;538
57.2;2. Behavioral Modeling in VHDL;539
57.3;3 . Modeling the Simulation Kernel;540
57.4;4. An Example;546
57.5;5. Discussion;549
57.6;Acknowledgments;549
57.7;6.References;550
58;Chapter 38."Checking DFT Rules with a VHDL Simulator";552
58.1;1 Introduction;552
58.2;2 Basic Principle;553
58.3;3 Checking Rules for Synchronous Design;553
58.4;4 Checking Rules for Modular Testing Support;558
58.5;5 Possible Extensions to Some Other Applications;562
58.6;6 Limitations;563
58.7;7 Conclusions;564
58.8;Acknowledgements;564
58.9;References;564
59;Chapter 39."Parameterized VHDL entities for the simulation of hybrid circuits";566
59.1;1. Introduction;566
59.2;2. Signal representation in RAMSES;567
59.3;3. Contents of the RAMSES libraries;569
59.4;4. Complete example;576
59.5;5. Current limitations;581
59.6;6. Future work;581
59.7;7. Conclusion;582
59.8;8. Literature;582
60;Chapter 40."Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models";584
60.1;1. INTRODUCTION;584
60.2;2. MODELING PRINCIPLE;585
60.3;3. MODELING TECHNIQUE;587
60.4;4. VHDL IMPLEMENTATION OF GATE MODELS;591
60.5;5. PARAMETER EXTRACTION AND SIMULATION;595
60.6;6. MODELING EXAMPLE;598
60.7;7. CONCLUSIONS;601
60.8;REFERENCES;601
61;Chapter 41."Analog-VHDL: As an application, a real example";602
61.1;I. Introduction;602
61.2;II. Synchronization of Algorithms;603
61.3;III. The mixed interface;604
61.4;IV. MINT-Sugar;605
61.5;V. Presentation of analog-VHDL;605
61.6;VI. A complete example;610
61.7;VIL Conclusion;619
61.8;Acknowledgements;619
61.9;BIBLIOGRAPHY;619