Silicon Based Unified Memory Devices and Technology

1. Auflage 2017
ISBN: 978-1-138-74632-9
Verlag: Taylor & Francis Ltd

Buch, Englisch, 544 Seiten, Format (B × H): 178 mm x 254 mm, Gewicht: 1315 g

The primary focus of this book is on basic device concepts, memory cell design, and process technology integration. The first part provides in-depth coverage of conventional nonvolatile memory devices, stack structures from device physics, historical perspectives, and identifies limitations of conventional devices. The second part reviews advances made in reducing and/or eliminating existing limitations of NVM device parameters from the standpoint of device scalability, application extendibility, and reliability. The final part proposes multiple options of silicon based unified (nonvolatile) memory cell concepts and stack designs (SUMs). The book provides Industrial R&D personnel with the knowledge to drive the future memory technology with the established silicon FET-based establishments of their own. It explores application potentials of memory in areas such as robotics, avionics, health-industry, space vehicles, space sciences, bio-imaging, genetics etc.

Zielgruppe

Academic and Professional Practice & Development

Autoren/Hrsg.

Bhattacharyya, Arup

Fachgebiete

• Technische Wissenschaften Energietechnik | Elektrotechnik Elektrotechnik
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise

Inhaltsverzeichnis

PART I CONVENTIONAL SILICON BASED NVM DEVICES. SILICON BASED DIGITAL MEMORIES AND NVMs: AN INTRODUCTORY OVERVIEW. HISTORICAL PROGRESSION OF NVM DEVICES. GENERAL PROPERTIES OF DIELECTRICS AND INTERFACE FOR NVM DEVICES. ELECTRIC FILMS FOR NVM DEVICES. NVM UNIQUE DEVICE PROPERTIES. NVM DEVICE STACK DESIGN. NVM CELLS, ARRAYS AND DISTURBS. NVM PROCESS TECHNOLOGY AND INTEGRATION SCHEME. NVM DEVICE RELIABILITY. CONVENTIONAL NVM CHALLENGES. PART II ADVANCED NVM DEVICES AND TECHNOLOGY. VOLTAGE SCALABILITY. HIGH-K DIELECTRICS FILMS FOR NVM. BAND ENGINEERING FOR NVM DEVICES. ENHANCED TECHNOLOGY INTEGRATION FOR NVM. PLANAR MULTILEVEL STORAGE NVM DEVICES. NON PLANAR AND 3D DEVICES AND ARRAYS. EMERGING NVMs & LIMITATIONS OF CURRENT NVM DEVICES. ADVANCED SILICON-BASED NVM DEVICE CONCEPTS. PART III: SUM: SILICON BASED UNIFIED MEMORY. SUM PERSPECTIVE, DEVICE CONCEPTS AND POTENTIALS. SUM TECHNOLOGY. BAND ENGINEERING FOR SUM DEVICES. UNIFUNCTIONAL SUM: THE USUM CELLS AND ARRAY. MULTIFUNCTIONAL SUM: THE MSUM CELLS AND ARRAYS. SUM FUNCTIONAL INTEGRATION, PACKAGING AND POTENTIAL APPLICATION.

Über Autor(innen)

Dr. Arup Bhattacharyya has forty years of leadership and pioneering contributions in the area of microelectronics and nanoelectronics. He has contributed pioneering activities and innovations in process, device, interconnect, and integration of many generations of microelectronics and nano-electronics. His inventions include nearly 300 U.S. and international Patents and invention publications in technologies such as CCD, BIPOLAR, FET, NVM, FLASH, ANTIFUSE, SOI, BICMOS, SOLAR-CELLS, and SOC. Some of the applications of Dr. Bhattacharyya's inventions include electronic Memories, Microprocessors and Controllers, Random and Programmable Logic Devices, Nonvolatile Devices, Energy-conversion devices, ASICs, ASDs, and SMART Electronic Devices. He has experience in R&D leadership, Program management and Technology transfer, Technical Education and Consultancy, Strategic Planning, Infrastructure Development, Product Development, and Manufacturability. Additional experiences include University teaching, volunteering for science and engineering promotion, service to professional organizations, and consultancy to the UN.