Borrione Advances in Design Methods from Modeling Languages for Embedded Systems and SoC's

Selected Contributions on Specification, Design, and Verification from FDL 2009
1. Auflage 2010
ISBN: 978-90-481-9304-2
Verlag: Springer-Verlag
Format: PDF
Kopierschutz: Wasserzeichen (»Systemvoraussetzungen)

E-Book, Englisch, 248 Seiten

More than ever, FDL is the place for researchers, developers, industry designers, academia, and EDA tool companies to present and to learn about the latest scientific achievements, practical applications and users experiences in the domain of specification and design languages. FDL covers the modeling and design methods, and their latest supporting tools, for complex embedded systems, systems on chip, and heterogeneous systems. FDL 2009 is the twelfth in a series of events that were held all over Europe, in selected locations renowned for their Universities and Reseach Institutions as well as the importance of their industrial environment in Computer Science and Micro-electronics. In 2009, FDL was organized in the attractive south of France area of Sophia Antipolis. together with the DASIP (Design and Architectures for Signal and Image Processing) Conference and the SAME (Sophia Antipolis MicroElectronics ) Forum. All submitted papers were carefully reviewed to build a program with 27 full and 10 short contributions. From these, the Program Committee selected a shorter list, based on the evaluations of the reviewers, and the originality and relevance of the work that was presented at the Forum. The revised, and sometimes extended versions of these contributions constitute the chapters of this volume. Advances in Design Methods from Modeling Languages for Embedded Systems and SoC's presents extensions to standard specification and description languages, as well as new language-based design techniques and methodologies to solve the challenges raised by mixed signal and multi-processor systems on a chip. It is intended as a reference for researchers and lecturers, as well as a state of the art milestone for designers and CAD developers.

Autoren/Hrsg.

Borrione, Dominique

Inhaltsverzeichnis

1;Preface;6
2;Contents;8
3;Part I UML and MDE for Embedded Systems;10
3.1;Chapter 1:IP-XACT Components with Abstract Time Characterization;11
3.1.1;1. Introduction;11
3.1.2;2. Related Work;14
3.1.3;3. MARTE CCSL;14
3.1.4;4. Example -- AHB to APB Bridge;15
3.1.4.1;Informal Specification;16
3.1.4.2;CCSL Specification;17
3.1.5;5. Comparing RTL and TLM Implementations;21
3.1.6;6. Conclusions;23
3.1.7;References;24
3.2;Chapter 2:MDE Support for HW/SW Codesign: A UML-based Design Flow;27
3.2.1;1. Introduction;27
3.2.2;2. State-of-the-Art and Related Works;29
3.2.2.1;Hardware/Software Co-design;30
3.2.2.2;Related Work;32
3.2.3;3. Theoretical Context;33
3.2.4;4. Codesign-Driven Modeling: Integrated Design Flow;34
3.2.4.1;Design Rules;35
3.2.4.2;Mathematical Formalization and MARTE;36
3.2.4.3;Co-design Analysis;37
3.2.5;5. Code Generation: from MARTE Models to SystemC;38
3.2.5.1;Architectural Extensions;39
3.2.5.2;Translation Rules;40
3.2.6;6. Case Study;40
3.2.7;7. Conclusions and Future Works;42
3.2.8;References;43
4;Part II C/C++-Based System Design;46
4.1;Chapter 3:Checkpoint and Restore for SystemC Models;48
4.1.1;1. Introduction;49
4.1.1.1;Checkpointing Implementation Issues;50
4.1.2;2. Simics Checkpointing Basics;51
4.1.3;3. SystemC in Simics;53
4.1.4;4. Checkpointing SystemC Model State;54
4.1.4.1;Model Requirements;54
4.1.4.2;SystemC Parameters to Simics Attributes;54
4.1.4.3;Limitations;55
4.1.5;5. Checkpointing SystemC Kernel State;56
4.1.6;6. Related Work;57
4.1.7;7. Experiments;58
4.1.7.1;Simics-SystemC Bridge Performance;58
4.1.7.2;SystemC Checkpoint Support Overhead;59
4.1.7.3;Validating Basic Checkpointing;59
4.1.7.4;Validating Model Updates;60
4.1.7.5;Checkpoint Size;60
4.1.7.6;Complex Test Case;61
4.1.8;8. Discussion;62
4.1.9;9. Conclusions;63
4.1.10;References;63
4.2;Chspter 4:Efficient Approximately-Timed Performance Modeling for Architectural Exploration of MPSoCs;65
4.2.1;1. Introduction;65
4.2.2;2. Related Work;67
4.2.3;3. Temporal Abstraction Levels;69
4.2.4;4. Modeling;70
4.2.4.1;Application Modeling;70
4.2.4.2;Modeling MPSoC Architectures;71
4.2.4.3;Setting the Mapping Constraints;72
4.2.5;5. Performance Evaluation;73
4.2.5.1;Activation-Based Execution;73
4.2.5.2;Transaction-Based Communication;74
4.2.5.3;Performance Evaluation;75
4.2.6;6. Case Study: Motion-JPEG Decoder;76
4.2.6.1;Design Space Exploration;76
4.2.6.2;Transaction Delays;76
4.2.7;7. Conclusions;77
4.2.8;References;77
4.3;Chapter 5: Fast SystemC Performance Models for the Exploration of Embedded Memories;79
4.3.1;1. Introduction;79
4.3.2;2. The Memory Design Space;81
4.3.3;3. Related Work;81
4.3.4;4. Exploration Framework;82
4.3.4.1;Representation of Data and Storage;83
4.3.4.2;Performance Simulation;83
4.3.4.3;Analysis of a Memory Hierarchy;84
4.3.5;5. Memory Models;85
4.3.5.1;Single Access Model;86
4.3.5.2;Grouped Access Model;86
4.3.5.3;Iterated Contention Algorithm;88
4.3.6;6. Quality of Memory Models;89
4.3.6.1;Impact of Access Distributions;89
4.3.6.2;Comparison of Access Models;90
4.3.6.3;Accuracy of Access Models;91
4.3.6.4;Simulation Performance;93
4.3.7;7. Case Study;94
4.3.7.1;Impact of Memory Subsystem;94
4.3.7.2;Application and Memory Mappings;94
4.3.7.3;Discussion;96
4.3.8;8. Conclusion;97
4.3.9;Acknowledgment;97
4.3.10;References;97
4.4;Chapter 6:Another Take on Functional System-Level Design and Modeling;99
4.4.1;1. Introduction;99
4.4.2;2. State of the Art;100
4.4.3;3. Overview;101
4.4.3.1;Engine/MoC Dichotomy;101
4.4.3.2;Data Exchange Between MoCs;102
4.4.3.3;MoC Design;102
4.4.3.4;Engine Design;103
4.4.4;4. Examples;104
4.4.4.1;Instrumentation;104
4.4.4.2;Evaluation of Memory Access Costs for Tomographic Reconstruction;106
4.4.4.2.1;Cache Memory Models;106
4.4.4.2.2;User Specified Design;106
4.4.4.2.3;Performance Discussion;108
4.4.5;5. Conclusion;111
4.4.6;References;111
4.5;Chapter 7:Design Automation Model for Application-Specific Processors on Reconfigurable Fabric;113
4.5.1;1. Introduction;113
4.5.2;2. Languages for Customizable Processors;115
4.5.3;3. RH(+) Model;116
4.5.3.1;Abstraction of Low-Level Details for Instruction Set;116
4.5.3.2;Flexible Operator Definition;117
4.5.3.3;Flexible Data Types;118
4.5.3.4;Configurability and Self-Retargettable Compiler;119
4.5.3.5;Constraints Setting;119
4.5.4;4. Implementation of RH(+);119
4.5.4.1;FRH(+);120
4.5.4.2;LRH(+);121
4.5.4.3;Constraints and Configurability;122
4.5.4.4;Instruction Selection and Generation;123
4.5.4.5;Compiler;124
4.5.5;5. Illustrative Example;125
4.5.6;6. Conclusions and Future Work;129
4.5.7;Acknowledgment;129
4.5.8;References;129
4.6;Chspter 8: A SystemC Superset for High-Level Synthesis;131
4.6.1;1. Introduction;131
4.6.2;2. SystemC Synthesizable Superset;133
4.6.2.1;HLS Modules;133
4.6.2.2;HLS Interfaces;134
4.6.2.2.1;Interface Object Types;135
4.6.2.3;HLS Threads;136
4.6.2.4;HLS Shared Variables;137
4.6.2.5;Schedule Object and Timing Annotation Points;137
4.6.3;3. Timing Accuracy Levels;139
4.6.3.1;Approximately-Timed Simulation Mode;139
4.6.3.2;Cycle-Accurate at the Transactions Boundaries (CATB) Simulation Mode;139
4.6.3.3;Loosely-Timed Simulation Mode;139
4.6.3.4;Un-timed Simulation Mode;140
4.6.4;4. Design Flow;140
4.6.5;5. Results;140
4.6.6;6. Conclusions;143
4.6.7;References;143
5;Part III Embedded Analog and Mixed-Signal System Design;145
5.1;Chapter 9:Design of Experiments for Effective Pre-silicon Verification of Automotive Electronics;146
5.1.1;1. Introduction;146
5.1.2;2. State of the Art;147
5.1.3;3. Design of Experiments;149
5.1.4;4. Approach;150
5.1.4.1;Objective;150
5.1.4.2;Abstract Description;151
5.1.4.3;Implementation;153
5.1.5;5. Results;154
5.1.5.1;System Overview;154
5.1.5.2;Implementation;155
5.1.5.3;(1) System Monte Carlo (MC);156
5.1.5.4;(2) Two-Level Full Factorial (DoE1);158
5.1.5.5;(3) Multi-level Full Factorial (DoE2);158
5.1.5.6;(4) Response Surface DoE -- CCD (DoE3);160
5.1.5.7;Discussion;161
5.1.6;6. Conclusion;162
5.1.7;Acknowledgement;162
5.1.8;References;163
5.2;Chspter 10:A VHDL-AMS Modeling Methodology for Top-Down/Bottom-Up Design of RF Systems;164
5.2.1;1. Introduction;165
5.2.2;2. Modeling Methodology;167
5.2.2.1;Specifications for the Frequency Synthesizer;168
5.2.2.2;Design, Implementation, and Test of the Frequency Synthesizer;173
5.2.3;3. Usage of the RF_TRX Library in the Design Process of a Binary FSK Transmitter;177
5.2.3.1;Implementation of the FSK Transmitter Model;177
5.2.3.2;Simulation of Different Transmitter Design Cases;178
5.2.4;4. Conclusions and Outlook;182
5.2.5;Acknowledgment;183
5.2.6;References;183
6;Part IV Assertion Based Design, Verification & Debug;185
6.1;Chspter 11:High Level Synthesis Using Operation Properties;186
6.1.1;1. Introduction;186
6.1.2;2. Previous Work;187
6.1.3;3. Operation Properties;188
6.1.4;4. Synthesis Algorithm;190
6.1.5;5. Results;195
6.1.6;6. Conclusion;196
6.1.7;References;196
6.2;Chapter 12:A Re-Use Methodology for Formal SoC Protocol Compliance Verification;199
6.2.1;1. Introduction;200
6.2.2;2. Verification Methodology;202
6.2.3;3. Formal Protocol Specification;204
6.2.3.1;Bus Recorder;204
6.2.3.2;Properties;208
6.2.4;4. Experimental Results;210
6.2.4.1;Recorder Versus Monitor;210
6.2.4.2;Checking Protocol Compliance with Standard Property Checking Techniques;211
6.2.4.3;Checking Protocol Compliance Using IPC and Reachability Analysis;211
6.2.4.3.1;Reachability Analysis;211
6.2.4.3.2;Verifying Properties Using IPC;212
6.2.5;5. Conclusion;213
6.2.6;References;213
6.3;Chapter 13:ISIS: Runtime Verification of TLM Platforms;215
6.3.1;1. Introduction;215
6.3.2;2. A Framework for the ABV of TLM Models;216
6.3.2.1;Monitoring TLM Descriptions -- Principles;217
6.3.2.2;Discussion About the ``Next' Operator;218
6.3.3;3. Using the Boolean and Modeling Layers;218
6.3.3.1;Boolean Layer: C++ Predicates;218
6.3.3.2;Modeling Layer: Auxiliary Variables;219
6.3.4;4. The ISIS Tool;220
6.3.5;5. Experimental Results;221
6.3.5.1;Producers/Consumer with a FIFO Channel;222
6.3.5.2;DMA System;223
6.3.5.3;Protocol over Faulty Channel;224
6.3.5.4;Packet Switch;225
6.3.5.5;Motion-JPEG Case Study;225
6.3.6;6. Related Work;226
6.3.7;7. Conclusion;227
6.3.8;Notes;227
6.3.9;References;227
6.4;Chapter 14:SMT-based Stimuli Generation in the SystemC Verification Library;229
6.4.1;1. Introduction;229
6.4.2;2. Preliminaries;231
6.4.2.1;SystemC Verification Library;231
6.4.2.2;SAT Modulo Theory;232
6.4.3;3. SMT-Based Stimuli Generation;233
6.4.3.1;Limits of BDDs;233
6.4.3.2;Integrating SAT Modulo Theories;234
6.4.4;4. Distribution of Generated Stimuli;236
6.4.4.1;Determine Distributed Solutions;236
6.4.4.2;Choosing Solutions;238
6.4.4.3;Handling Overconstraining;239
6.4.5;5. Experimental Evaluation;239
6.4.6;6. Conclusions and Future Work;243
6.4.7;Notes;244
6.4.8;References;244
7;Index;247