Chatterjee / Pun / Stanic Analog Circuit Design Techniques at 0.5V

1. Auflage 2010
ISBN: 978-0-387-69954-7
Verlag: Springer-Verlag
Format: PDF
Kopierschutz: Adobe DRM (»Systemvoraussetzungen)

E-Book, Englisch, 158 Seiten

Analog design at ultra-low supply voltages is an important challenge for the semiconductor research community and industry.

covers challenges for the design of MOS analog and RF circuits at a 0.5 V power supply voltage. All design techniques presented are true low voltage techniques - all nodes in the circuits are within the power supply rails. The circuit implementations of body and gate input fully differential amplifiers are also discussed. These building blocks enable us to build continuous-time filters, track-and-hold circuits, and continuous-time sigma delta modulators.

Current books on low voltage analog design typically cover techniques for supply voltages down to approximately 1V. This book presents novel ideas and results for operation from much lower supply voltages and the techniques presented are basic circuit techniques that are widely applicable beyond the scope of the presented examples.

is written for analog circuit designers and researchers as well as graduate students studying semiconductors and integrated circuit design.

Autoren/Hrsg.

Chatterjee, Shouri

Pun, K.P.

Stanic, Nebojša

Tsividis, Yannis

Kinget, Peter

Inhaltsverzeichnis

1;Preface;7
2;Contents;8
3;1 Introduction;11
3.1;1.1 Low-voltage analog cir cuit design challenges;14
3.2;1.2 Opportunities at low voltages;19
3.3;1.3 Organization of the book;24
4;2 Fully Differential Operational Transconductance Amplifiers (O T As);26
4.1;2.1 Body-input O T A;28
4.2;2.2 Gate-input O T A;32
4.3;2.3 On-chip biasing circuits for the gate-input O T A;38
4.4;2.4 Characterization results for the body-input and gate-input O T A s;44
4.5;2.5 Discussion on the two O T A design techniques;48
4.6;2.6 Design methodology for low V;50
4.7;2.7 Summary;54
5;3 Weak Inversion MOS Varactors for Tunable Integrators;57
5.1;3.1 Brief theoretical overview;58
5.2;3.2 Device measur ements and modeling;58
5.3;3.3 Circuit applications;64
5.4;3.4 Summary;68
6;4 A 0.5 V 5th-Order Low-Pass Elliptic Filter;69
6.1;4.1 Filter topology;69
6.2;4.2 On-chip PLL-based automatic frequency tuning loop;70
6.3;4.3 Lay out and prototype chip;73
6.4;4.4 Characterization Results;74
6.5;4.5 Summary;79
7;5 A 0.5 V Track-and-Hold (T/H) Circuit;84
7.1;5.1 Introduction;84
7.2;5.2 T/H operation at ultra-low voltages;84
7.3;5.3 Fully-differ ential 0.5 V T/H cir cuit;86
7.4;5.4 Design details and measurement results;93
7.5;5.5 Conclusion;99
8;6 A 0.5 V Continuous-Time Modulator;103
8.1;6.1 Introduction;103
8.2;6.2 Return-to-Open DAC;104
8.3;6.3 Split RTO DAC Modulator Architecture;109
8.4;6.4 Building Block Circuits for 0.5 V Supply;114
8.5;6.5 Experimental Results;118
8.6;6.6 Conclusions;126
9;7 0.5 V Receiver Front-End Circuits;127
9.1;7.1 Introduction;127
9.2;7.2 RF Receiver System-Level Considerations;127
9.3;7.3 Low-Noise Amplifiers;128
9.4;7.4 Downcon version Mixers;130
9.5;7.5 900 MHz Receiver Front-End in 0.18 µ m C M O S;133
10;A Analysis of a Distributed Model for a MOS Capacitor;146
11;References;152
12;Index;160