Electronic Devices Architectures for the NANO-CMOS Era

1. Auflage 2008
ISBN: 978-981-4241-28-1
Verlag: Pan Stanford

Buch, Englisch, 425 Seiten, Format (B × H): 152 mm x 229 mm, Gewicht: 816 g

In this book, internationally recognized researchers give a state-of-the-art overview of the electronic device architectures required for the nano-CMOS era and beyond. The book covers the fundamental limits of core CMOS, improving scaling by the introduction of new materials or processes, multigates and multichannels, and quantum computing.

Zielgruppe

Academic and Postgraduate

Autoren/Hrsg.

Deleonibus, Simon

Fachgebiete

• Technische Wissenschaften Maschinenbau | Werkstoffkunde Technische Mechanik | Werkstoffkunde
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik
• Naturwissenschaften Biowissenschaften Biowissenschaften

Inhaltsverzeichnis

CMOS Nanoelectronics. Reaching the End of the Roadmap: Core CMOS: Physical and Technological Limitations of NanoCMOS Devices to the End of the Roadmap and Beyond. Advanced CMOS Devices on Bulk and SOI: Physics, Modeling and Characterization. Devices Structures and Carrier Transport Properties of Advanced CMOS using High Mobility Channels. High-kappa Gate Dielectrics. Fabrication of Source and Drain — Ultra Shallow Junction. New Interconnect Schemes: End of Copper, Optical Interconnects? Memory Devices: Technologies and Key Design Issues for Memory Devices. FeRAM and MRAM Technologies. Advanced Charge Storage Memories: From Silicon Nanocrystals to Molecular Devices. New Concepts for Nanoelectronics. New Paths Added to CMOS Beyond the End of the Roadmap: Single Electron Devices and Applications. Electronic Properties of Organic Monolayers and Molecular Devices. Carbon Nanotube Electronics. Spin Electronics. The Longer Term: Quantum Information Processing and Communication.

Über Autor(innen)

Simon Deleonibus (MSc 1979, PhD 1982, Paris University) was with Thomson Semiconducteurs, Grenoble, France, from 1981 to 1986 in device engineering development and then production. In 1986 he was with CEA LETI advanced device and process modules research specialising in CMOS and flash memories applications. From 1998 to 2008 he was the director of the Electronic Nanodevices Laboratory with 55 researchers under his charge. Since 2008, he is the chief scientific director of Silicon Technologies of LETI. He owns the initial patent on contact plug principle, widely used as a standard process by the semiconductor industry. He actualised the first 20-nm gate length MOSFET, the world’s smallest transistor, in June 1999. He is the editor of IEEE Transactions on Electron Devices and a member of the International Technology Roadmap of Semiconductors (ITRS), of the board of directors of the Nanosciences Foundation and of The European Research Council Engineering Panel. A Fellow of the IEEE, he is its distinguished lecturer. He is also the research director of the French CEA.