Deleonibus Electronic Devices Architectures for the NANO-CMOS Era

1. Auflage 2011
ISBN: 978-981-4241-29-8
Verlag: Pan Stanford Publishing
Format: PDF
Kopierschutz: Adobe DRM (»Systemvoraussetzungen)

E-Book, Englisch, 426 Seiten

In this book, internationally recognized researchers give a state-of-the-art overview of the electronic device architectures required for the nano-CMOS era and beyond. Challenges relevant to the scaling of CMOS nanoelectronics are addressed through different core CMOS and memory device options in the first part of the book. The second part reviews new device concepts for nanoelectronics beyond CMOS. The book covers the fundamental limits of core CMOS, improving scaling by the introduction of new materials or processes, new architectures using SOI, multigates and multichannels, and quantum computing.

Zielgruppe

Microelectronics and nanoelectronics engineers and physicists interested in the scaling down of CMOS devices and in considering possible alternatives to CMOS.

Autoren/Hrsg.

Deleonibus, Simon

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik

Inhaltsverzeichnis

CMOS Nanoelectronics. Reaching the End of the Roadmap
Core CMOS
Physical and Technological Limitations of NanoCMOS Devices to the End of the Roadmap and Beyond, S Deleonibus, O Faynot, B de Salvo, T Ernst, C Le Royer, T Poiroux & M Vinet
Advanced CMOS Devices on Bulk and SOI: Physics, Modeling and Characterization, T Poiroux & G Le Carval
Devices Structures and Carrier Transport Properties of Advanced CMOS using High Mobility Channels, S Takagi, T Tezuka, T Irisawa, S Nakaharai, T Numata, K Usuda, N Sugiyama, M Shichijo, R Nakane & S Sugahara
High-kappa Gate Dielectrics, H Wong, K Shiraishi, K Kakushima & H Iwai
Fabrication of Source and Drain — Ultra Shallow Junction, B Mizuno
New Interconnect Schemes: End of Copper, Optical Interconnects? S Laval, L Vivien, E Cassan, D Marris-Morini & J-M Fédéli

Memory Devices
Technologies and Key Design Issues for Memory Devices, K Kim & G Jeong
FeRAM and MRAM Technologies, Y Arimoto
Advanced Charge Storage Memories: From Silicon Nanocrystals to Molecular Devices, B De Salvo & G Molas

New Concepts for Nanoelectronics. New Paths Added to CMOS Beyond the End of the Roadmap
Single Electron Devices and Applications, J Gautier, X Jehl & M Sanquer
Electronic Properties of Organic Monolayers and Molecular Devices, D Vuillaume
Carbon Nanotube Electronics, V Derycke, A Filoramo & J-P Bourgoin
Spin Electronics, K-J Lee & S H Lim
The Longer Term: Quantum Information Processing and Communication, P Jorrand

Über Autor(innen)

Simon Deleonibus (MSc 1979, PhD 1982, Paris University) was with Thomson Semiconducteurs, Grenoble, France, from 1981 to 1986 in device engineering development and then production. In 1986 he was with CEA LETI advanced device and process modules research specialising in CMOS and flash memories applications. From 1998 to 2008 he was the director of the Electronic Nanodevices Laboratory with 55 researchers under his charge. Since 2008, he is the chief scientific director of Silicon Technologies of LETI. He owns the initial patent on contact plug principle, widely used as a standard process by the semiconductor industry. He actualised the first 20-nm gate length MOSFET, the world’s smallest transistor, in June 1999. He is the editor of IEEE Transactions on Electron Devices and a member of the International Technology Roadmap of Semiconductors (ITRS), of the board of directors of the Nanosciences Foundation and of The European Research Council Engineering Panel. A Fellow of the IEEE, he is its distinguished lecturer. He is also the research director of the French CEA.