Intelligent Integrated Systems

Devices, Technologies, and Architectures
1. Auflage 2014
ISBN: 978-981-4411-42-4
Verlag: Jenny Stanford Publishing

Buch, Englisch, 516 Seiten, Format (B × H): 157 mm x 235 mm, Gewicht: 890 g

Reihe: Jenny Stanford Series on Intelligent Nanosystems

A state-of-the-art overview by internationally recognized researchers, this book reviews the architectures of breakthrough devices required for future intelligent integrated systems. It highlights advanced ailicon-based CMOS technologies. New device and functional architectures are reviewed in chapters on Tunneling Field-Effect Transistors and 3-D monolithic Integration, which the alternative materials could possibly use in the future. It illustrates how to augment silicon technologies by the co-integration of new types of devices, such as molecular and resistive spintronics-based memories and smart sensors, using nanoscale features co-integrated with silicon CMOS or above it.

Zielgruppe

Academic and Postgraduate

Autoren/Hrsg.

Deleonibus, Simon

Fachgebiete

• Technische Wissenschaften Maschinenbau | Werkstoffkunde Technische Mechanik | Werkstoffkunde Materialwissenschaft: Elektronik, Optik
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Mikroprozessoren
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Elektronische Baugruppen, Elektronische Materialien
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Transistoren

Inhaltsverzeichnis

Advanced Silicon-Based CMOS Technologies. From Planar to Trigate and Nanowires Fully Depleted Transistors. Schottky Source/Drain MOSFETs. Advances in Silicon-On-Diamond Technology. GeOI, SiGeOI and New Devices Architectures. 3D Monolithic Integration. III-V Quantum-Well FETs. Carbon Integrated Electronics. New Paths to Augmented Silicon CMOS Technologies. Tunneling Field-Effect Transistors – Challenges and Perspectives. Molecular Memories. Resistive Memories. High frequency vibrating nanowire. Spintronics. Smart Multiphysics Sensors. 3D Integration and Wafer Level Packaging.

Über Autor(innen)

Simon Deleonibus retired from CEA-LETI on January 1, 2016, as chief scientist after 30 years of research on the architecture of micro- and nanoelectronic devices. Before joining CEA-LETI, he was with Thomson Semiconductors (1981–1986), where he developed and transferred to production advanced microelectronic devices and products. He obtained his PhD in applied physics from Paris University (1982). He is a visiting professor at Tokyo Institute of Technology (Tokyo, Japan) since 2014, National Chiao Tung University (Hsinchu, Taiwan) since 2015, and Chinese Academy of Science (Beijing, PRC) since 2016. A recipient of several awards and honors, and erstwhile associate editor of the IEEE Transactions on Electron Devices (2008-2014), Prof. Deleonibus is research director of the CEA since 2002, a distinguished lecturer at IEEE since 2004, and a fellow of the IEEE since 2006 and of the Electrochemical Society since 2015.