Elgamel Interconnect Noise Optimization in Nanometer Technologies

1. Auflage 2006
ISBN: 978-0-387-29366-0
Verlag: Springer-Verlag
Format: PDF
Kopierschutz: Adobe DRM (»Systemvoraussetzungen)

E-Book, Englisch, 137 Seiten

Interconnect has become the dominating factor in determining system performance in nanometer technologies. Dedicated to this subject, Interconnect Noise Optimization in Nanometer Technologies provides insight and intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits.

The authors bring together a wealth of information presenting a range of CAD algorithms and techniques for synthesizing and optimizing interconnect. Practical aspects of the algorithms and the models are explained with sufficient details. The book investigates the most effective parameters in layout optimization. Different post-layout optimization techniques with complexity analysis and benchmarks tests are provided. The impact crosstalk noise and coupling on the wire delay is analyzed. Parameters that affect signal integrity are also considered.

Autoren/Hrsg.

Elgamel, Mohamed

Inhaltsverzeichnis

1;Contents;6
2;LIST OF FIGURES;10
3;LIST OF TABLES;13
4;Preface;14
5;Acknowledgments;16
6;Chapter 1 INTRODUCTION;17
6.1;1.1 TECHNOLOGY TRENDS;17
6.2;1.2 MOTIVATION;18
6.3;1.3 BOOK OUTLINE;18
7;Chapter 2 NOISE ANALYSIS AND DESIGN IN DEEP SUBMICRON;20
7.1;2.1 NOISE;21
7.2;2.2 RELIABILITY;23
7.3;2.3 NOISE SOURCES;24
7.4;2.4 NOISE REDUCTION TECHNIQUES;28
7.5;2.5 NOISE ANALYSIS ALGORITHMS;40
8;Chapter 3 INTERCONNECT NOISE ANALYSIS AND OPTIMIZATION TECHNIQUES;44
8.1;3.1. SILICON TECHNOLOGY;44
8.2;3.2. INTERCONNECT NOISE MODELS;47
8.3;3.3. INTERCONNECT NOISE MINIMIZATION TECHNIQUES;50
8.4;3.4. INTERCONNECT NOISE IN EARLY DESIGN STAGES;53
8.5;3.5. CASE STUDY: PENTIUM® 4;57
9;Chapter 4 CROSSTALK NOISE ANALYSIS IN ULTRA DEEP SUBMICROMETER TECHNOLOGIES;59
9.1;4.1 ANALYTICAL EXPRESSIONS;60
9.2;4.2 TRANSMISSION LINE MODEL ;60
9.3;4.3 SIMULATION RESULTS;64
9.4;4.4 DESIGN GUIDELINES;70
9.5;4.5 SUMMARY;71
10;Chapter 5 MINIMUM AREA SHIELD INSERTION FOR INDUCTIVE NOISE REDUCTION;72
10.1;5.1 INDUCTIVE COUPLING;72
10.2;5.2 PROBLEM FORMULATION ;75
10.3;5.3 SHIELD INSERTION ALGORITHM;79
10.4;5.4 EXPERIMENTAL RESULTS;83
10.5;5.5 COMPLEXITY ANALYSIS;86
10.6;5.6 SUMMARY;86
11;Chapter 6 SPACING ALGORITHMS FOR CROSSTALK NOISE REDUCTION;87
11.1;6.1 SIMULTANEOUS WIRE SIZING AND WIRE SPACING IN POST- LAYOUT;87
11.2;6.2 POST GLOBAL ROUTING CROSSTALK SYNTHESIS;88
11.3;6.3 TIMING- AND CROSSTALK-DRIVEN AREA ROUTING;89
11.4;6.4 A SPACING ALGORITHM FOR PERFORMANCE ENHANCEMENT AND CROSSTALK REDUCTION;89
11.5;6.5 A POST PROCESSING ALGORITHM FOR CROSSTALK- DRIVEN WIRE PERTURBATION;90
12;Chapter 7 POST LAYOUT INTERCONNECT OPTIMIZATION FOR CROSSCOUPLING NOISE REDUCTION;91
12.1;7.1 MOTIVATIONS;92
12.2;7.2 PROBLEM FORMULATION;93
12.3;7.3 NOISE MODELING;94
12.4;7.4 MULTI SEGMENT NETS CROSSCOUPLING NOISE MODEL;98
12.5;7.5 MULTI CROSSCOUPLING NOISE MODEL;99
12.6;7.6 WIRE SPACING;100
12.7;7.7 POST LAYOUT RE-SPACING ALGORITHM;101
12.8;7.8 EXPERIMENTAL RESULTS;103
12.9;7.9 SUMMARY;105
13;Chapter 8 3D INTEGRATION;106
13.1;8.1 EXISTING 3D INTEGRATION TECHNOLOGIES;106
13.2;8.2 COMMERCIAL 3D DEVICES;108
13.3;8.3 3D IC DESIGN TOOLS;109
14;Chapter 9 EDA INDUSTRY TOOLS: STATE OF THE ART;117
14.1;9.1 MENTOR GRAPHICS;117
14.2;9.2 CADENCE;120
14.3;9.3 SYNOPSYS;129
14.4;9.4 ACCELERANT NETWORKS INC. ;131
14.5;9.5 SILICON METRICS ;132
14.6;9.6 MAGMA ;132
15;Index;141
16;About the Authors;143