Fair Rapid Thermal Processing

Science and Technology
1. Auflage 2012
ISBN: 978-0-323-13980-9
Verlag: Elsevier Science & Techn.
Format: EPUB
Kopierschutz: 6 - ePub Watermark

E-Book, Englisch, 430 Seiten

This is the first definitive book on rapid thermal processing (RTP), an essential namufacturing technology for single-wafer processing in highly controlled environments. Written and edited by nine experts in the field, this book covers a range of topics for academics and engineers alike, moving from basic theory to advanced technology for wafer manufacturing. The book also provides new information on the suitability or RTP for thin film deposition, junction formation, silicides, epitaxy, and in situ processing. Complete discussions on equipment designs and comparisons between RTP and other processing approaches also make this book useful for supplemental information on silicon processing, VLSI processing, and integrated circuit engineering.

Autoren/Hrsg.

Fair, Richard B.

Inhaltsverzeichnis

1;Front Cover;1
2;Rapid Thermal Processing: Science and Technology;4
3;Copyright Page;5
4;Table of Contents;6
5;Contributors;9
6;Chapter 1. Rapid Thermal Processing—A Justification;10
6.1;I. Manufacturing Issues in the Gigachip Age;10
6.2;II. The Parameter Budget Crisis;12
6.3;III. Conclusions;19
6.4;References;19
7;Chapter 2. Rapid Thermal Processing–Based Epitaxy;22
7.1;I. Introduction to Silicon Epitaxy;24
7.2;II. Characteristics of Rapid Thermal Processing-Based Silicon Epitaxy;34
7.3;III. Growth of Strained Silicon–Germanium Alloys;40
7.4;IV. Summary;49
7.5;References;50
8;Chapter 3. Rapid Thermal Growth and Processing of Dielectrics;54
8.1;I. Equipment Issues in Rapid Thermal Oxidation;56
8.2;II. Rapid Thermal Oxidation Growth Kinetics;60
8.3;III. Rapid Thermal Processing of Oxides;67
8.4;IV. Electrical Properties of Rapid Thermal Oxidation/Rapid Thermal Processing Oxides;71
8.5;V. Conclusions;81
8.6;Acknowledgments;81
8.7;References;82
9;Chapter 4. Thin-Film Deposition;88
9.1;I. Equipment;90
9.2;II. Thin-Film Deposition Processes;92
9.3;III. In Situ Processing—Applications;115
9.4;IV. Equipment Issues;120
9.5;V. Summary;127
9.6;References;127
10;Chapter 5. Extended Defects from Ion Implantation and Annealing;132
10.1;I. Introduction;132
10.2;II. Defect Formation Kinetics;142
10.3;III. Defect Annealing Kinetics;164
10.4;IV. Summary;171
10.5;References;172
11;Chapter 6. Junction Formation in Silicon by Rapid Thermal Annealing;178
11.1;I. Rapid Thermal Annealing of Ion-Implanted Junctions;183
11.2;II. Dopant Activation;222
11.3;III. Summary and Conclusions;229
11.4;References;230
12;Chapter 7. Silicides;236
12.1;I. Introduction;237
12.2;II. Formation of Silicides;249
12.3;III. Properties of Silicides and Silicided Junctions;273
12.4;IV. Applications of Silicides Formed by RTA and Process/Device Considerations;291
12.5;V. Summary;301
12.6;References;301
13;Chapter 8. Issues in Manufacturing Unique Silicon Devices Using Rapid Thermal Annealing;320
13.1;I. Impact of Patterned Layers on Temperature Nonuniformity during Rapid Thermal Annealing;323
13.2;II. Bipolar Transistor Processing;334
13.3;III. MOS Transistor Processing;346
13.4;IV. Conclusion;353
13.5;References;355
14;Chapter 9. Manufacturing Equipment Issues in Rapid Thermal Processing;358
14.1;I. Historical Survey of Rapid Thermal Processing;360
14.2;II. Fundamental Thermophysics in Rapid Thermal Processing;361
14.3;III. General Rapid Thermal Processing System Components;368
14.4;IV. Survey of Commercial Rapid Thermal Processing Equipment;390
14.5;V. Temperature Nonuniformity, System Modeling, and Effective Emissivity;399
14.6;VI. Noncontact In Situ Real-Time Process Control Options;410
14.7;VII. Recent Developments and Future Trends in Rapid Thermal Processing;416
14.8;VIII. Technology Roadmap and Concluding Remarks;423
14.9;Acknowledgments;426
14.10;References;426
15;Index;434

Leseproben

2

Rapid Thermal Processing–Based Epitaxy

J.L. Hoyt    Solid State Electronics Laboratory, Stanford, California

I. Introduction to Silicon Epitaxy   15

A. Role of Silicon Epitaxy In Integrated Circuit Technology   15

B. Conventional Epitaxial Growth Processes   17

C. Important Properties of Epitaxial Silicon   18

D. Advanced Epitaxial Growth Techniques   20

E. Rapid Thermal Processing–Based Epitaxial Reactors   23

II. Characteristics of Rapid Thermal Processing-Based Silicon Epitaxy   25

A. Growth Kinetics   25

B. Doping Profile Abruptness   27

C. Material Quality   29

III. Growth of Strained Silicon-Germanium Alloys   31

A. Device Applications   33

B. Growth Basics   33

C. Heterojunction Bipolar Transistors   35

D. Misfit Dislocations   37

IV. Summary   40

References   41

Epitaxial growth of silicon and silicon related materials using rapid thermal processing (RTP) techniques is a rapidly growing field. Compared to other applications of rapid thermal processing such as annealing or oxidation, epitaxial growth is one of the most progressive, and hence less well-developed areas. Work in this area began in the mid-1980s with the development of the limited reaction processing (LRP) technique by Gibbons and Gronet at Stanford University [1]. This technique combines rapid thermal processing and chemical vapor deposition (CVD). In early work on LRP, the wafer temperature, rather than the flow of reactive gases, was used to initiate and terminate layer growth. Limited reaction processing has been used to grow multilayer structures consisting of thin layers of n- and p-type Si [2], silicon/oxide/polysilicon structures [3], and thin Si1 –x Gex layers, with thicknesses in the range of tens to hundreds of angstroms [4]. The technique has also been applied to the epitaxial growth of III–V compounds [5, 6].

In addition to the pioneering work on LRP at Stanford, research on epitaxial growth using rapid thermal processing techniques appeared in the literature in the late 1980s and early 1990s under the name of rapid thermal chemical vapor deposition (RTCVD) [7, 8], rapid transient epitaxy [9], rapid thermal processing chemical vapor deposition (RTPCVD) [10], as well as various photon and plasma assisted single-wafer processes [11]. One feature of such work is the growth of multiple layers without removing the wafer from the process chamber, thereby reducing the potential for interfacial contamination. Another key attribute is the ability to optimize the growth temperature for each layer in a complicated structure, since wafer temperature can be changed as readily as gas flows. Thermal exposure of the substrate is inherently minimized. The equipment employs lamp heating of individual wafers. The absence of a thick graphite susceptor allows for rapid changes in wafer temperature, and reduces memory effects from layer to layer and wafer to wafer. Such reactors are designed to minimize wall deposition, which reduces memory effects as well as particulate problems associated with flaking. In this chapter we lump together all CVD techniques that involve single-wafer epitaxy, in which rapid changes of wafer temperature can be achieved by lamp heating, under the heading of “rapid thermal processing applied to epitaxy.” This is a natural grouping for a book on rapid thermal processing, since the differences between the various techniques mentioned above are more subtle than the distinction between RTP-based epitaxy and other growth techniques such as molecular beam epitaxy or ultrahigh vacuum chemical vapor deposition, which are discussed in Section I D.

Among the various physical processes involved in silicon integrated circuit fabrication, the growth of thin crystalline silicon layers on silicon wafers (“epitaxy”) is the most demanding in terms of the requirements placed on the processing environment and equipment. In epitaxial growth, a perfect replication of the crystal structure of each atomic layer is required. However, there is a natural tendency for defects to form, particularly at low growth temperatures. The growth of epitaxial silicon layers with high electrical quality and precise thickness and doping control is a challenge that imposes constraints on all epitaxial growth equipment. Constraints related to characteristics such as ambient purity, vacuum compatibility, wall deposition, and processing time imply that a rapid thermal processor suitable for epitaxial growth will look different from one that is designed for annealing or suicide formation. Hence, this chapter begins with a brief review of general considerations for silicon-based epitaxy. Requirements for conventional and advanced epitaxy are discussed, and the various forms of advanced epitaxy are compared. Section II reviews the characteristics of RTP-based silicon epitaxy. The third section discusses a particular application for which RTP is well suited, namely epitaxial growth of Si and Si1–xGex layers for heterojunction bipolar transistors.

I Introduction to Silicon Epitaxy

This section briefly reviews conventional epitaxial growth applications, and the important properties of silicon epitaxial layers are listed. Various advanced epitaxial growth techniques are introduced in Section I D. For a general discussion of silicon epitaxial growth, the reader is referred to Chapter 2 of VLSI Technology [12].

A ROLE OF SILICON EPITAXY IN INTEGRATED CIRCUIT TECHNOLOGY

Silicon epitaxy provides a means of controlling doping profiles beyond what can be achieved using diffusion and ion implantation. In its original application, epitaxy solved competing device requirements for low collector resistance and capacitance, as well as high breakdown voltages in bipolar transistors [13]. A lightly doped epitaxial silicon layer, which provides a lower base-collector breakdown voltage, is grown upon a heavily doped “buried layer” or substrate, which lowers the collector resistance and improves frequency performance. The evolution of epitaxial silicon technology as applied to bipolar transistors is shown in Fig. 1. The doping profile in Fig. la illustrates an npn bipolar transistor of the 1970s, including a 6 µm-thick n- epitaxial Si layer grown on a heavily doped buried layer. The p-type base and n+ Si emitter were typically formed by diffusing impurities from the surface into the lightly doped epitaxial Si. A typical bipolar transistor of the 1980s is shown in Fig. 1b, with a thin ion-implanted base layer. The thickness of the Si epitaxial layer, and in particular the thickness of the lightly doped collector region, is scaled considerably compared to transistors of the 1970s. A hypothetical doping profile for a fully scaled bipolar transistor is shown in Fig. 1c. All three regions (collector, base, and emitter) are formed by an advanced epitaxial growth technique.

Figure 1 The evolution of vertical doping profiles in Si bipolar transistors: (a) 1970s, (b) 1980s, and (c) advanced transistor.

Epitaxial layers are also used in metal oxide semiconductor (MOS) technology to reduce alpha particle and latch-up problems [14], and in bipolar complementary MOS (BICMOS) applications. Selective epitaxial growth offers the potential to improve the performance of bipolar and MOS circuits [15]. However, the majority of applications of epitaxial silicon still consist of a single lightly doped layer, with thickness in the range of 1 to 10 µm. Highly advanced applications seek to provide arbitrary doping profiles, with thicknesses ranging from tens of angstroms up to several micrometers.

B CONVENTIONAL EPITAXIAL GROWTH PROCESSES

Chemical vapor deposition of epitaxial silicon is usually performed in a quartz reaction chamber with a number of wafers placed flat against a silicon carbide coated, graphite susceptor. Deposition takes place with the wafers held at elevated temperature while a gas mixture consisting of purified hydrogen and a silicon source gas is flowed into the reactor. Silane and dichlorosilane are typical silicon source gases. Hydrides such as phosphine and diborane can be added to dope the layers during growth. Hydrogen provides the required gas velocity, dilutes unwanted impurities, and participates in various surface reactions. The details of the chemical reactions involved in silicon epitaxial growth are still not completely understood. However, the overall...