Girard / Nicolici / Wen Power-Aware Testing and Test Strategies for Low Power Devices

1. Auflage 2010
ISBN: 978-1-4419-0928-2
Verlag: Springer-Verlag
Format: PDF
Kopierschutz: Adobe DRM (»Systemvoraussetzungen)

E-Book, Englisch, 363 Seiten

Managing the power consumption of circuits and systems is now considered one of the most important challenges for the semiconductor industry. Elaborate power management strategies, such as dynamic voltage scaling, clock gating or power gating techniques, are used today to control the power dissipation during functional operation. The usage of these strategies has various implications on manufacturing test, and power-aware test is therefore increasingly becoming a major consideration during design-for-test and test preparation for low power devices. This book explores existing solutions for power-aware test and design-for-test of conventional circuits and systems, and surveys test strategies and EDA solutions for testing low power devices.

Autoren/Hrsg.

Girard, Patrick

Nicolici, Nicola

Wen, Xiaoqing

Inhaltsverzeichnis

1;Summary and Objective of the Book;5
2;About the Editors;6
3;Preface;8
4;Contents;12
5;Contributors;21
6;1 Fundamentals of VLSI Testing;22
6.1;1.1 Introduction;22
6.2;1.2 Fault Models;26
6.3;1.3 Design for Testability;28
6.3.1;1.3.1 Ad Hoc Methods;28
6.3.2;1.3.2 Scan Design;31
6.3.3;1.3.3 Built-In Self-Test;32
6.3.4;1.3.4 Test Compression;34
6.4;1.4 Logic Testing;36
6.5;1.5 Memory Testing;40
6.6;1.6 System-On-Chip Testing;44
6.7;1.7 Summary and Conclusions;46
6.8;References;47
7;2 Power Issues During Test;51
7.1;2.1 Introduction;51
7.2;2.2 Power and Energy Basics;53
7.2.1;2.2.1 Static Dissipation;53
7.2.1.1;2.2.1.1 Reverse-Biased pn Junction Leakage Current;54
7.2.1.2;2.2.1.2 Sub-threshold Leakage Current;54
7.2.1.3;2.2.1.3 Gate Leakage Current;55
7.2.1.4;2.2.1.4 Gate-Induced Drain Leakage Current;56
7.2.2;2.2.2 Dynamic Dissipation;57
7.2.2.1;2.2.2.1 Dynamic Dissipation Due to Charging and Discharging of Load Capacitors;57
7.2.2.2;2.2.2.2 Dynamic Dissipation Due to Short-Circuit Current;59
7.2.3;2.2.3 Total Power Dissipation;60
7.2.4;2.2.4 Energy Dissipation;60
7.3;2.3 Manufacturing Test Flow;61
7.3.1;2.3.1 Characterization Test;61
7.3.2;2.3.2 Production Test;61
7.3.3;2.3.3 Burn-in Test;61
7.3.4;2.3.4 Incoming Inspection;62
7.3.5;2.3.5 Typical Test Flow;62
7.4;2.4 Power Delivery Issues During Test;63
7.4.1;2.4.1 Packaging;64
7.4.2;2.4.2 Power Grid Issues;66
7.4.3;2.4.3 Power Supply Noise;66
7.4.3.1;2.4.3.1 Low-Frequency Power Droop;67
7.4.3.2;2.4.3.2 Mid-Frequency Power Droop;68
7.4.3.3;2.4.3.3 High-Frequency Power Droop;68
7.4.3.4;2.4.3.4 Voltage Drop During At-Speed Scan;69
7.5;2.5 Thermal Issues During Test;70
7.6;2.6 Test Throughput Problem;72
7.6.1;2.6.1 Limited Power Availability During Wafer Sort Test;72
7.6.2;2.6.2 Reduction in Test Frequency During Package Test;73
7.6.3;2.6.3 Constraint on Simultaneous Testing of Multiple Cores;73
7.6.4;2.6.4 Noisy Power Supply During Wafer Sort Test;73
7.7;2.7 Manufacturing Yield Loss;74
7.7.1;2.7.1 ATE Timing Inaccuracy;74
7.7.2;2.7.2 Application of Illegal Test Vectors;75
7.8;2.8 Test Power Metrics and Estimation;76
7.8.1;2.8.1 Power Metrics;77
7.8.2;2.8.2 Modeling of Power and Energy Metrics;77
7.8.3;2.8.3 Test Power Estimation;79
7.9;2.9 Summary;80
7.10;References;81
8;3 Low-Power Test Pattern Generation;84
8.1;3.1 Introduction;84
8.2;3.2 Low-Power ATPG;86
8.2.1;3.2.1 General Low-Power Test Generation;86
8.2.2;3.2.2 Low-Shift-Power Scan Test Generation;87
8.2.3;3.2.3 Low-Capture-Power Scan Test Generation;88
8.2.3.1;3.2.3.1 Capture-Safety Checking;91
8.2.3.2;3.2.3.2 LCP ATPG Technique 1: Reversible Backtracking;93
8.2.3.3;3.2.3.3 LCP ATPG Technique 2: Clock Manipulation;94
8.3;3.3 Low-Power Test Compaction;97
8.3.1;3.3.1 Low-Power Dynamic Compaction;97
8.3.2;3.3.2 Low-Power Static Compaction;98
8.3.2.1;3.3.2.1 Low-Shift-Power Static Compaction;98
8.3.2.2;3.3.2.2 Low-Capture-Power Static Compaction;99
8.4;3.4 Low-Power X-Filling;100
8.4.1;3.4.1 Test Cube Preparation;101
8.4.1.1;3.4.1.1 Direct Generation;101
8.4.1.2;3.4.1.2 Test Relaxation;102
8.4.2;3.4.2 Low-Shift-Power X-Filling;106
8.4.2.1;3.4.2.1 Shift-In Power Reduction;107
8.4.2.2;3.4.2.2 Shift-Out Power Reduction;108
8.4.2.3;3.4.2.3 Total Shift Power Reduction;108
8.4.3;3.4.3 Low-Capture-Power X-Filling;109
8.4.3.1;3.4.3.1 FF-Oriented X-Filling;109
8.4.3.2;3.4.3.2 Node-Oriented X-Filling;114
8.4.3.3;3.4.3.3 Critical-Area-Oriented X-Filling;116
8.4.4;3.4.4 Low-Shift-and-Capture-Power X-Filling;116
8.4.4.1;3.4.4.1 Impact-Oriented X-Filling;117
8.4.4.2;3.4.4.2 X-Distribution-Controlled Test Relaxation and Hybrid X-Filling;118
8.4.4.3;3.4.4.3 Bounded Adjacent Fill;120
8.4.5;3.4.5 Low-Power X-Filling for Compressed Scan Testing;120
8.4.5.1;3.4.5.1 X-Filling for Code-Based Test Compression;121
8.4.5.2;3.4.5.2 X-Filling for Linear-Decompressor-Based Test Compression;123
8.4.5.3;3.4.5.3 X-Filling in Broadcast-Based TestCompression;124
8.5;3.5 Low-Power Test Ordering;124
8.5.1;3.5.1 Internal-Transition-Based Ordering;124
8.5.2;3.5.2 Inter-Vector-Hamming-Distance-Based Ordering;125
8.5.3;3.5.3 Input-Transition-Density-Based Ordering;126
8.6;3.6 Low-Power Memory Test Generation;127
8.6.1;3.6.1 Address Switching Activity Reduction;127
8.6.2;3.6.2 Precharge Restriction;128
8.7;3.7 Summary and Conclusions;129
8.8;References;130
9;4 Power-Aware Design-for-Test;135
9.1;4.1 Introduction;135
9.2;4.2 Power Consumption in Scan Design;136
9.2.1;4.2.1 Power Consumption of the Circuit Under Test;136
9.2.2;4.2.2 Types of Power Consumption in Scan Testing;137
9.3;4.3 Low-Power Scan Cells;139
9.3.1;4.3.1 Power Considerations of Standard Scan Cells;139
9.3.2;4.3.2 Scan Clock Gating;140
9.3.3;4.3.3 Test Planning for Scan Clock Gating;143
9.3.4;4.3.4 Toggle Suppression;145
9.4;4.4 Scan Path Organization;146
9.4.1;4.4.1 Scan Path Segmentation;147
9.4.2;4.4.2 Extended Clock Schemes for Scan Segmentation;149
9.4.3;4.4.3 Scan Cell Clustering;151
9.4.4;4.4.4 Scan Cell Ordering;152
9.4.5;4.4.5 Scan Tree and Scan Forest;154
9.4.6;4.4.6 Inserting Logic into the Scan Path;156
9.5;4.5 Partitioning for Low Power;157
9.5.1;4.5.1 Partitioning by Clock Gating;158
9.5.2;4.5.2 Partitioning in Core-Based Design;159
9.5.3;4.5.3 Partitioning of the Combinational Logic;160
9.6;4.6 Summary and Conclusions;161
9.7;References;162
10;5 Power-Aware Test Data Compression and BIST;165
10.1;5.1 Introduction;165
10.2;5.2 Coding-Based Compression Methods;168
10.2.1;5.2.1 Golomb Code;168
10.2.2;5.2.2 Alternating Run-Length Code;170
10.2.3;5.2.3 Recent Advances in Coding-Based Compression Methods;172
10.3;5.3 LFSR-Decompressor-Based Compression Methods;175
10.4;5.4 Broadcast-Scan-Based Compression Methods;176
10.5;5.5 Low-Power BIST Techniques;177
10.5.1;5.5.1 Vector Inhibition and Selection;180
10.5.2;5.5.2 Modified TPG;181
10.5.3;5.5.3 Modified Scan and Reordering;185
10.5.4;5.5.4 Test Scheduling;186
10.6;5.6 Summary and Conclusions;187
10.7;References;187
11;6 Power-Aware System-Level Test Planning;192
11.1;6.1 Introduction;192
11.2;6.2 Core-Based Test Architecture Design and Test Planning;195
11.2.1;6.2.1 Core Test Wrapper;196
11.2.2;6.2.2 Test Access Mechanism Design;197
11.2.3;6.2.3 Test Scheduling;198
11.3;6.3 Power Modeling, Estimation, and Manipulation;200
11.3.1;6.3.1 Modeling Power Consumption and Constraints;202
11.3.1.1;6.3.1.1 Power Modeling;202
11.3.1.2;6.3.1.2 Power Constraint Modeling;204
11.3.2;6.3.2 Power Estimation;205
11.3.3;6.3.3 Power Manipulation;208
11.3.3.1;6.3.3.1 Power-Aware Wrapper Design;209
11.3.3.2;6.3.3.2 Ordering of Test Data;210
11.4;6.4 Power-Constrained Test Planning;211
11.4.1;6.4.1 Power-Constrained Test Scheduling;212
11.4.2;6.4.2 Power-Aware Test Architecture Design and Test Scheduling;215
11.4.3;6.4.3 Power-Constrained Test Planning Utilizing Power-Aware DfT;217
11.4.3.1;6.4.3.1 DfT for Shift-Power Reduction;217
11.4.3.2;6.4.3.2 DfT for Capture-Power Reduction;218
11.5;6.5 Hierarchical Test Planning Strategies for SOCs;219
11.5.1;6.5.1 Low-Power Test Planning for Multiple Clock Domains;219
11.5.2;6.5.2 IDDQ Test Planning for Core-Based System Chips;221
11.6;6.6 Summary;223
11.7;References;224
12;7 Low-Power Design Techniques and Test Implications;229
12.1;7.1 Introduction;229
12.2;7.2 Low-Power Design Trends;232
12.2.1;7.2.1 Dynamic Power Reduction Techniques;232
12.2.1.1;7.2.1.1 Circuit Optimization for Low Power;232
12.2.1.2;7.2.1.2 Clock Gating;233
12.2.1.3;7.2.1.3 Operand Isolation;233
12.2.1.4;7.2.1.4 Advanced Power and Thermal Management;234
12.2.2;7.2.2 Leakage Power Reduction Techniques;235
12.2.2.1;7.2.2.1 Input Vector Control;235
12.2.2.2;7.2.2.2 Dual-Vth Design;236
12.2.2.3;7.2.2.3 Supply Gating;237
12.2.2.4;7.2.2.4 Shannon Cofactoring-Based Dynamic Supply Gating;238
12.2.2.5;7.2.2.5 Leakage Control in Memory;239
12.3;7.3 Power Specification Format;239
12.4;7.4 Implications to Test Requirement and Test Cost;242
12.4.1;7.4.1 Impact of Dynamic Power Reduction Techniques on Test;242
12.4.1.1;7.4.1.1 Static Design-Time Techniques;242
12.4.1.2;7.4.1.2 Dynamic Power Reduction Techniques;243
12.4.2;7.4.2 Impact of Leakage Power Reduction Techniques on Test;244
12.4.2.1;7.4.2.1 Leakage Reduction Using IVC;244
12.4.2.2;7.4.2.2 Shannon Decomposition-Based Logic Synthesis;244
12.4.2.3;7.4.2.3 Leakage Reduction in Memory;244
12.4.2.4;7.4.2.4 Thermal Stability During Burn-In;245
12.5;7.5 Low-Power Design Techniques for Test Power and Coverage Improvement;245
12.6;7.6 Self-Calibrating and Self-Correcting Systems for Power-Related Failure Detection;250
12.6.1;7.6.1 Self-Calibration and Repair in Logic Circuits;250
12.6.1.1;7.6.1.1 RAZOR;250
12.6.1.2;7.6.1.2 Body Biasing and Effect on Delay Test;251
12.6.1.3;7.6.1.3 Process Compensation in Dynamic Circuits;252
12.6.1.4;7.6.1.4 Delay Calibration;253
12.6.2;7.6.2 Self-Repairing SRAM;253
12.7;7.7 Summary and Conclusions;255
12.8;References;255
13;8 Test Strategies for Multivoltage Designs;259
13.1;8.1 Introduction;259
13.2;8.2 Test for Multivoltage Design: Bridge Defect;260
13.2.1;8.2.1 Resistive Bridge Behavior at Single-Vdd Setting;261
13.2.2;8.2.2 Resistive Bridge Behavior at Multi-Vdd Settings;264
13.2.3;8.2.3 Cost-Effective Test for Resistive Bridge;267
13.2.3.1;8.2.3.1 Test Point Insertion;268
13.2.3.2;8.2.3.2 Gate Sizing;268
13.3;8.3 Test for Multivoltage Design: Open Defect;271
13.3.1;8.3.1 Testing Full-Open Defect;271
13.3.2;8.3.2 Testing Resistive Open Defect;274
13.4;8.4 DFT for Low-Power Design;277
13.4.1;8.4.1 Multivoltage-Aware Scan;277
13.4.2;8.4.2 Power-Managed Scan Using Adaptive Voltage Scaling;279
13.5;8.5 Open Research Problems;281
13.5.1;8.5.1 Impact of Voltage and Process Variation on Test Quality;281
13.5.2;8.5.2 Diagnosis for Multivoltage Designs;282
13.5.3;8.5.3 Voltage Scaling for Nanoscale SRAM;283
13.6;8.6 Summary and Conclusions;284
13.7;References;284
14;9 Test Strategies for Gated Clock Designs;288
14.1;9.1 Introduction;288
14.2;9.2 DFT for Clock Gating Logic;291
14.2.1;9.2.1 Safe Gating of Clocks in Edge Sensitive Designs;291
14.2.2;9.2.2 Edge Sensitive, MUXed Scan;291
14.2.3;9.2.3 LSSD;295
14.2.4;9.2.4 Advanced DFT with On-Product Clock Generation (OPCG);296
14.2.5;9.2.5 Overriding of Functional Clock Gating;297
14.3;9.3 Taking Advantage of Clock Gating;297
14.3.1;9.3.1 Locating Where Clocks are Gated;301
14.3.2;9.3.2 Identifying ``Default' Values;303
14.3.3;9.3.3 Dynamically Augmenting a Test;305
14.4;9.4 Summary and Conclusions;306
14.5;References;307
15;10 Test of Power Management Structures;309
15.1;10.1 Clock Gating Logic;309
15.1.1;10.1.1 Controlling Clock Gaters during Test;310
15.1.2;10.1.2 Impact on Testability of the Clock Gater and its Control Logic;310
15.1.3;10.1.3 Impact on Power and Pattern Count;311
15.2;10.2 Power Control Logic;312
15.2.1;10.2.1 Role of Power Control Logic;312
15.2.2;10.2.2 Power Control during Shift;313
15.2.3;10.2.3 Power Control during Capture;314
15.2.4;10.2.4 Testing the Power Control Logic;315
15.3;10.3 Power Switches;317
15.3.1;10.3.1 Types of Power Switches;318
15.3.2;10.3.2 Testing of Power Switches;319
15.3.3;10.3.3 Methodologies for Testing Power Switches;319
15.3.4;10.3.4 Testing Problems and Possible Solution;325
15.4;10.4 Low-Power Cells;326
15.4.1;10.4.1 State Retention Registers;326
15.4.2;10.4.2 Isolation Cells;327
15.4.3;10.4.3 Level Shifters;328
15.5;10.5 Power Distribution Network;328
15.5.1;10.5.1 PDN Structures;330
15.5.2;10.5.2 Open Defects in PDNs;331
15.5.3;10.5.3 Pattern Generation Procedure;332
15.6;10.6 Summary and Conclusions;335
15.7;References;335
16;11 EDA Solution for Power-Aware Design-for-Test;337
16.1;11.1 Introduction;337
16.2;11.2 Design Flows for Power Management;339
16.2.1;11.2.1 Multi-voltage and Power Gating Context;339
16.2.2;11.2.2 Unified Power Format;341
16.2.2.1;11.2.2.1 Creation of Power Domains;341
16.2.2.2;11.2.2.2 Top-Level Connections;341
16.2.2.3;11.2.2.3 Primary Power Nets;342
16.2.2.4;11.2.2.4 Creation and Mapping of Power Switch Cell;342
16.2.2.5;11.2.2.5 Definition of Isolation Strategy and Isolation Control;342
16.2.2.6;11.2.2.6 Retention Strategy and Retention Control in pd1;343
16.2.2.7;11.2.2.7 Power State Table;343
16.2.2.8;11.2.2.8 Level Shifter Strategy;343
16.3;11.3 Test Automation Objectives;344
16.3.1;11.3.1 Quality of Results;344
16.3.2;11.3.2 DFT Requirements in Mission Mode;344
16.3.3;11.3.3 Integration into Design Flows;345
16.4;11.4 Integration of Power Management Techniques in Design-for-Test Synthesis Flows;345
16.4.1;11.4.1 DFT for Low-Power Rules;346
16.4.1.1;11.4.1.1 Stability of Test Modes during Test;347
16.4.1.2;11.4.1.2 Controllability of Isolation Enables;348
16.4.1.3;11.4.1.3 Controllability of Retention Signals;348
16.4.1.4;11.4.1.4 Scan Architecting across Power Domains;348
16.4.1.5;11.4.1.5 Controllability of Power Switches;348
16.4.1.6;11.4.1.6 Power Mode to Test Mode Mapping;349
16.4.2;11.4.2 Handling of State Retention Registers;349
16.4.3;11.4.3 Impact on DFT Architecture;351
16.4.3.1;11.4.3.1 User Control;351
16.4.3.2;11.4.3.2 Minimizing Domains Crossing;351
16.4.3.3;11.4.3.3 Impact on Scan Chain Reordering;352
16.4.4;11.4.4 Impact on DFT Implementation;354
16.4.4.1;11.4.4.1 Re-use of LS and ISO Cells during Scan Stitching;354
16.4.4.2;11.4.4.2 Automatic Insertion of LS and ISO Cells;355
16.4.4.3;11.4.4.3 Design Synthesis Flow Impact;356
16.4.5;11.4.5 Power Annotation and Hierarchical Design Flows;356
16.4.5.1;11.4.5.1 Low-Power Annotation;357
16.4.5.2;11.4.5.2 Scan Modeling Enhancement;357
16.4.5.3;11.4.5.3 Voltage Annotation for DFT Insertion;357
16.4.5.4;11.4.5.4 Power Domain Annotation for DFT Insertion;358
16.5;11.5 Test Planning;359
16.5.1;11.5.1 Predictability of Results;359
16.5.2;11.5.2 Power Dissipation vs. Test Application Time;360
16.5.3;11.5.3 Need for Multi-mode DFT Architecture;360
16.5.4;11.5.4 Test Scheduling Considerations;362
16.5.4.1;11.5.4.1 User Power Mode to Test Mode Mapping;362
16.5.4.2;11.5.4.2 ATPG Requirements;364
16.6;11.6 Summary and Conclusions;365
16.7;References;366
17;Summary;368
18;Index;370