Gupta Copper Interconnect Technology

1. Auflage 2010
ISBN: 978-1-4419-0076-0
Verlag: Springer-Verlag
Format: PDF
Kopierschutz: Adobe DRM (»Systemvoraussetzungen)

E-Book, Englisch, 423 Seiten

Since overall circuit performance has depended primarily on transistor properties, previous efforts to enhance circuit and system speed were focused on transistors as well. During the last decade, however, the parasitic resistance, capacitance, and inductance associated with interconnections began to influence circuit performance and will be the primary factors in the evolution of nanoscale ULSI technology. Because metallic conductivity and resistance to electromigration of bulk copper (Cu) are better than aluminum, use of copper and low-k materials is now prevalent in the international microelectronics industry. As the feature size of the Cu-lines forming interconnects is scaled, resistivity of the lines increases. At the same time electromigration and stress-induced voids due to increased current density become significant reliability issues. Although copper/low-k technology has become fairly mature, there is no single book available on the promise and challenges of these next-generation technologies. In this book, a leader in the field describes advanced laser systems with lower radiation wavelengths, photolithography materials, and mathematical modeling approaches to address the challenges of Cu-interconnect technology.

Autoren/Hrsg.

Gupta, Tapan

Inhaltsverzeichnis

1;Preface;6
2;Acknowledgments;9
3;Author Biography;15
4;1 Introduction;16
4.1;1.1 Trends and Challenges;17
4.2;1.2 Physical Limits and Search for New Materials;20
4.3;1.3 Challenges;21
4.4;1.4 Choice of Materials;22
4.4.1;1.4.1 Why Copper (Cu) Interconnects?;22
4.4.1.1;1.4.1.1 Line Resistivity;23
4.4.1.2;1.4.1.2 Efficiency of Cu-Lines versus Node Technology;25
4.4.1.3;1.4.1.3 Heat Dissipation;25
4.4.1.4;1.4.1.4 Electromigration (EM) Failure;26
4.4.1.5;1.4.1.5 Thermo-Mechanical Properties;27
4.4.1.6;1.4.1.6 Stress Migration Effect;29
4.5;1.5 New Technologies;30
4.5.1;1.5.1 Multilayer Metal Architecture;30
4.5.2;1.5.2 Substrate Engineering;31
4.6;1.6 An Alternate Technology for Interconnects;34
4.7;1.7 Materials Used in Modern Integrated Circuits;36
4.7.1;1.7.1 Properties of Copper;38
4.7.2;1.7.2 Grain Size;39
4.7.3;1.7.3 Melting Temperature;40
4.8;1.8 Barrier Layer;42
4.9;1.9 Low-K Dielectric Materials;43
4.10;1.10 Polymers;45
4.11;1.11 Semiconductors;47
4.11.1;1.11.1 Silicon (Si);48
4.12;1.12 Challenges and Accomplishments;49
4.12.1;1.12.1 Challenges;50
4.12.2;1.12.2 Accomplishments;50
4.13;1.13 Technologies of the 21st Century, and the Plan to Meet the Challenges;53
4.14;1.14 Ultra-Shallow Junction (USJ);54
4.15;1.15 Circuit Design and Architecture Improvements;56
4.16;1.16 Performance and Leakage in Low Standby Power (LSTP) Systems;56
4.17;1.17 Introduction of New Materials and Integration Processes;57
4.17.1;1.17.1 Nano-Materials;59
4.17.2;1.17.2 Superconductors;60
4.17.3;1.17.3 Integration Processes;62
4.17.3.1;1.17.3.1 3-D Technology;62
4.17.3.2;1.17.3.2 Air Gap Technology;63
4.17.3.3;1.17.3.3 Fabrication Status of Sub-Micron (65 nm and Below) Devices and Reliability Issues;65
4.18;1.18 Summary;68
5;2 Dielectric Materials;81
5.1;2.1 Introduction;81
5.2;2.2 Interlayer Dielectric (ILD);85
5.2.1;2.2.1 Introduction;85
5.2.1.1;2.2.1.1 Low-K;87
5.2.2;2.2.2 Mathematical Model;88
5.2.3;2.2.3 Selection Criteria for an Ideal Low-K Material;90
5.2.4;2.2.4 Search for an Ideal Low-K Material;92
5.2.4.1;2.2.4.1 Problems with Porous Films;96
5.2.4.2;2.2.4.2 Pore Sealing;97
5.2.5;2.2.5 Achievement;97
5.2.5.1;2.2.5.1 Porous Silicon Dioxide (SiO 2 ) (the Xerogel);97
5.2.5.2;2.2.5.2 Carbon Doped Oxide;97
5.2.5.3;2.2.5.3 Black Diamond;98
5.2.5.4;2.2.5.4 Bezocyclobutene (BCB) Based Polymer;99
5.2.5.5;2.2.5.5 Aromatic (Hydrocarbon) Thermosetting Polymer (ATP);100
5.2.5.6;2.2.5.6 Hydrogen Silesquioxanes (HSQ, HSiO 1.5 );101
5.2.5.7;2.2.5.7 Methyl Silsesquioxane (MSQ);103
5.2.5.8;2.2.5.8 Poly (Arylene Ethers) (PAE);104
5.2.5.9;2.2.5.9 Parylene;105
5.2.5.10;2.2.5.10 Teflon AF;105
5.2.5.11;2.2.5.11 Diamond-Like Carbon (DLC);105
5.2.6;2.2.6 Impact of Low-K ILD Materials on the Cu-Damascene Process;106
5.2.7;2.2.7 Deposition Techniques;109
5.2.7.1;2.2.7.1 Flow chart for Damascene Architecture;109
5.3;2.3 High-K Dielectric Materials;110
5.3.1;2.3.1 Introduction;111
5.3.2;2.3.2 Impact on Scaling and Requirements;112
5.3.3;2.3.3 Search for a Suitable High-K Dielectric Material;113
5.3.3.1;2.3.3.1 Nitrides and Oxynitrides;113
5.3.3.2;2.3.3.2 Tantalum Oxide (Ta 2 O 5 ) and Titanium Oxide (TiO 2 );114
5.3.3.3;2.3.3.3 Hafnium Oxide (HfO 2 );114
5.3.3.4;2.3.3.4 Zirconium Oxide (ZrO 2 );115
5.3.3.5;2.3.3.5 Lanthanum Aluminate (LaAlO 3 );115
5.3.3.6;2.3.3.6 Titanate Compounds of Barium (BaTiO 3 ), Barium Strontium (BaSrTiO 3 ), and Lead (PbTiO 3 );115
5.3.4;2.3.4 Deposition Technology for High-K Materials;116
5.3.5;2.3.5 Summary;116
6;3 Diffusion and Barrier Layers;125
6.1;3.1 Diffusion;125
6.1.1;3.1.1 Introduction;125
6.1.2;3.1.2 Transitional Effects;127
6.1.3;3.1.3 Mathematical Modeling of Diffusion in Cu-Interconnects;128
6.1.4;3.1.4 Grain Boundary (GB) Diffusion;132
6.1.5;3.1.5 Vacancy Diffusion;134
6.1.6;3.1.6 Drift Diffusion;135
6.1.7;3.1.7 Interdiffusion;136
6.1.8;3.1.8 Diffusion of Copper and Its Consequences;136
6.1.9;3.1.9 Precipitation;138
6.2;3.2 Barrier Layer for Cu-Interconnects;139
6.2.1;3.2.1 Theory;139
6.2.2;3.2.2 Ideal Barrier Layer;140
6.2.3;3.2.3 Barrier Layer Architecture;140
6.2.4;3.2.4 Interlayer Reactions;142
6.2.4.1;3.2.4.1 Case I: Single Barrier Layer;143
6.2.4.2;3.2.4.2 Case II: Double Layer Barrier Cu-Ta-TaN;146
6.2.5;3.2.5 Influence of the Barrier Layer Properties on the Reliability of Cu-Interconnects;146
6.2.5.1;3.2.5.1 Morphology of the Barrier Layer;146
6.2.5.2;3.2.5.2 Stress;147
6.2.5.3;3.2.5.3 Adhesion;148
6.2.6;3.2.6 Low-K Dielectric-Barrier Layer;149
6.2.7;3.2.7 Reaction Rates;149
6.2.7.1;3.2.7.1 Effect of Ambient;152
6.2.7.2;3.2.7.2 Processing Temperature;152
6.2.8;3.2.8 Influence of the Barrier Layer on the Electrical Conductivity of Cu-Lines;153
6.2.9;3.2.9 Influence of Barrier Layer Thermal Conductivity on Cu-Line;155
6.2.10;3.2.10 Classification of Barrier Layer;158
6.2.11;3.2.11 Properties of Different Barrier Layer Materials;159
6.2.11.1;3.2.11.1 Tantalum (Ta) and Its Compounds;159
6.2.11.2;3.2.11.2 Titanium(Ti) and Its Compounds;160
6.2.11.3;3.2.11.3 Molybdenum (Mo) and Its Compound;161
6.2.11.4;3.2.11.4 Tungsten (W) and Its Compounds;161
6.2.11.5;3.2.11.5 Cobalt;161
6.2.12;3.2.12 Cap-Layer, Its Properties and Functions;162
6.3;3.3 Summary;164
7;4 Pattern Generation;174
7.1;4.1 Photolithography;174
7.1.1;4.1.1 Introduction;174
7.1.2;4.1.2 Resolution Limits of Optical Lithography;177
7.1.2.1;4.1.2.1 Effect of the Media on Resolution;178
7.1.2.2;4.1.2.2 Effect of Wavelength Exposure on Resolution;179
7.1.2.3;4.1.2.3 Effect of Numerical Aperture (NA) on Resolution;179
7.1.2.4;4.1.2.4 Modulation Transfer Function and Critical Dimension (CD);179
7.1.2.5;4.1.2.5 Effects of Antireflective Coating (ARC) on Resolution;181
7.1.3;4.1.3 Deep Ultraviolet (DUV) Lithography;181
7.1.3.1;4.1.3.1 Technology for 193 nm Lithography;182
7.1.3.2;4.1.3.2 193 nm Exposure System;184
7.1.4;4.1.4 Reticles;186
7.1.5;4.1.5 Enhancement Techniques for Resolution;188
7.1.5.1;4.1.5.1 Antireflective Coating (ARC);188
7.1.5.2;4.1.5.2 Immersion Technique;189
7.1.5.3;4.1.5.3 Phase Shift Mask (PSM);190
7.1.6;4.1.6 157 nm Lithography;192
7.1.6.1;4.1.6.1 Wafer Exposure System;192
7.1.6.2;4.1.6.2 Optical System for 157 nm Resist;193
7.1.6.3;4.1.6.3 Reticle and Mask Systems for 157 nm Resist;195
7.1.6.4;4.1.6.4 Pellicles;196
7.1.7;4.1.7 Chemically Amplified Resist (CA);196
7.1.8;4.1.8 Extreme Ultraviolet (EUV) Lithography;198
7.1.9;4.1.9 e-Beam Lithography (EBL);202
7.1.10;4.1.10 Electron-Beam Resist;205
7.1.11;4.1.11 e-Beam Reticle;208
7.1.12;4.1.12 Step and Flash Imprint Lithography (SFIL);208
7.2;4.2 Etching and Cleaning of Damascene Structures;210
7.2.1;4.2.1 Etching;210
7.2.1.1;4.2.1.1 Advanced Process Technology;210
7.2.1.2;4.2.1.2 Process Chemistry of Etching;214
7.2.2;4.2.2 Cleaning;223
7.2.2.1;4.2.2.1 Introduction;223
7.3;4.3 Summary;226
8;5 Deposition Technologies of Materials for Cu-Interconnects;236
8.1;5.1 Introduction;236
8.2;5.2 Emerging Technologies;237
8.2.1;5.2.1 Cu-Damascene Process;237
8.2.2;5.2.2 Barrier Layer Requirements;238
8.3;5.3 Deposition Requirements;238
8.4;5.4 Thin Film Growth and Theory of Nucleation;239
8.4.1;5.4.1 Nucleation Theory;240
8.5;5.5 Instrumentation;242
8.5.1;5.5.1 Physical Vapor Deposition;243
8.5.2;5.5.2 Sputtering;244
8.5.2.1;5.5.2.1 DC and RF Sputtering Systems;245
8.5.2.2;5.5.2.2 Bias Sputtering;245
8.5.2.3;5.5.2.3 Magnetron Sputtering;246
8.5.2.4;5.5.2.4 Reactive Sputtering;246
8.5.3;5.5.3 Ionized Physical Vapor Deposition (IPVD);247
8.6;5.6 Chemical Vapor Deposition (CVD);249
8.6.1;5.6.1 Plasma Enhanced CVD (PECVD) System;249
8.6.2;5.6.2 Metal-Organic Vapor Deposition (MOCVD);251
8.7;5.7 Low Temperature Thermal CVD (LTTCVD) System;253
8.8;5.8 Atomic Layer Deposition (ALD);253
8.9;5.9 Plating;256
8.9.1;5.9.1 History of Electroplating and Printed Circuit Boards (PCBs);256
8.9.2;5.9.2 DC Bath Chemistry;257
8.9.3;5.9.3 Electroplating of Copper Inside Damascene Architecture;258
8.10;5.10 Process Chemistry for Superconformal Electrodeposition of Copper;260
8.11;5.11 Electrochemical Mechanical Deposition (ECMD);260
8.12;5.12 Influence of the Seed Layer on Electroplating;261
8.13;5.13 Electroless Deposition of Copper;263
8.14;5.14 Stress in Cu-Interconnects;263
8.15;5.15 Summary;265
9;6 The Copper Damascene Process and Chemical Mechanical Polishing;279
9.1;6.1 The Copper Damascene Process;279
9.1.1;6.1.1 Introduction;279
9.1.2;6.1.2 Conventional Metallization Technology;282
9.1.3;6.1.3 Cu-Damascene Metallization Technology;283
9.1.3.1;6.1.3.1 Different Approaches to Cu-Damascene Metallization;285
9.1.4;6.1.4 General Objectives and Challenges;288
9.2;6.2 Chemical Mechanical Polishing (CMP) and Planarization;290
9.2.1;6.2.1 Introduction;290
9.2.2;6.2.2 Chemical Mechanical Polishing (CMP)Technology;291
9.2.2.1;6.2.2.1 An Analytical Model;294
9.2.3;6.2.3 Copper Dishing Model;297
9.2.4;6.2.4 Slurry Chemistry;298
9.2.5;6.2.5 Particle Size Inside the Slurry;299
9.2.6;6.2.6 Relative Velocity of the Pad and Wafer;301
9.2.7;6.2.7 Pad Pressure;301
9.2.8;6.2.8 Pad-Elasticity;301
9.2.9;6.2.9 Pad Conditioning;301
9.2.10;6.2.10 Shallow Trench Isolation (STI);302
9.2.11;6.2.11 Abrasive Free Polishing;303
9.2.12;6.2.12 End-Point Detection;303
9.2.13;6.2.13 Dry In Dry Out;304
9.2.14;6.2.14 Multi-Step Processing;305
9.2.15;6.2.15 Post-CMP Cleaning;305
9.2.16;6.2.16 CMP Pattern Density Issues;307
9.3;6.3 Summary;307
10;7 Conduction and Electromigration;313
10.1;7.1 Conduction;313
10.1.1;7.1.1 Introduction;313
10.1.2;7.1.2 Conduction Mechanism and Restrictions;315
10.1.2.1;7.1.2.1 Scattering and Its Influence on Coductivity;316
10.1.2.2;7.1.2.2 Grain Boundary (GB) Scattering;320
10.1.2.3;7.1.2.3 Effective Resistance of Cu-Interconnect Due to Different Size of the Grains and the Presence of Barrier Layer;322
10.1.3;7.1.3 Effect of Grain Boundary (GB) Resistance on the Conductivity of Cu-Interconnects;323
10.1.4;7.1.4 Effect of Grain Size and Morphology of the Substrate;323
10.1.5;7.1.5 Morphology of the Cu-Film and Its Influence on the Conduction (Electrical) Mechanism of Cu-Interconnects;324
10.1.6;7.1.6 Effect of Film Thickness on the Conductivity of Cu-Interconnects;329
10.1.7;7.1.7 Diffusion Related Impacts on the Conductivity of a Cu-Line;330
10.1.8;7.1.8 Cu-Line Stress and Its Consequences;331
10.1.8.1;7.1.8.1 Stress Evolution Related Resistivity;332
10.1.9;7.1.9 Conduction of Heat Through Cu-Interconnects;333
10.1.10;7.1.10 Thermal Cycling (Annealing) Related Phenomena;334
10.2;7.2 Electromigration (EM);336
10.2.1;7.2.1 Electromigration (EM);336
10.2.2;7.2.2 Mechanism of Electromigration (EM) and Its Effects;337
10.2.3;7.2.3 Void Formation;341
10.2.4;7.2.4 Analytical Model on Stress Related EM;342
10.2.5;7.2.5 Effect of Microstructure of the Film on Mass Migration;345
10.2.6;7.2.6 Effect of Solute on Electromigration;347
10.2.7;7.2.7 Melting Temperature of a Metal and Its Effect on Grain Growth;347
10.2.8;7.2.8 Effect of Temperature on EM;348
10.2.9;7.2.9 Current Density and Its Effect on EM;348
10.3;7.3 Summary;348
11;8 Routing and Reliability;358
11.1;8.1 Routing;358
11.1.1;8.1.1 Introduction;358
11.1.2;8.1.2 Methods of Improving Interconnect Routings;360
11.1.2.1;8.1.2.1 Materials;360
11.1.2.2;8.1.2.2 Process Integration;362
11.1.2.3;8.1.2.3 Advanced Lithography;362
11.1.3;8.1.3 Interconnect Routing Design;362
11.1.3.1;8.1.3.1 Repeater Design;362
11.1.3.2;8.1.3.2 Bit Line;365
11.1.3.3;8.1.3.3 Scaling and Design;365
11.1.3.4;8.1.3.4 Manhattan Design;367
11.1.3.5;8.1.3.5 X-Architecture;367
11.1.3.6;8.1.3.6 Multilevel Design;369
11.1.4;8.1.4 Challenges with High Density Routing;370
11.1.4.1;8.1.4.1 Noise;370
11.1.4.2;8.1.4.2 Cross-Talk;370
11.1.5;8.1.5 Cascaded Driver;372
11.1.6;8.1.6 Transmission Line Coupling;372
11.1.7;8.1.7 Clocking of High-Speed System;372
11.2;8.2 Reliability;373
11.2.1;8.2.1 Introduction;373
11.2.2;8.2.2 Reliability Issues Related to Cu-Interconnects;376
11.2.2.1;8.2.2.1 Deposition Process Related Issues;376
11.2.2.2;8.2.2.2 Seed-Layer Related Reliability Issues;377
11.2.2.3;8.2.2.3 Oxidation Related Problems;378
11.2.2.4;8.2.2.4 Adhesion Problem;379
11.2.2.5;8.2.2.5 Scattering Related Reliability Issues;380
11.2.2.6;8.2.2.6 Joule Heating and Reliability Issues;381
11.2.2.7;8.2.2.7 Stress in Cu-Line and Its Effects on Reliability Issues;382
11.2.2.8;8.2.2.8 Thermal Stress and Related Phenomena;383
11.2.2.9;8.2.2.9 Blech Effect and Its Consequences;384
11.2.2.10;8.2.2.10 Reliability Problems Due to Electromigration (EM);385
11.2.2.11;8.2.2.11 Void Formation and Reliability Issues;387
11.2.2.12;8.2.2.12 Diffusion Related Problems;388
11.2.2.13;8.2.2.13 Reliability of the Barrier Layer;388
11.2.2.14;8.2.2.14 Presence of Via Holes and Trenches and Reliability Related Problems;390
11.2.2.15;8.2.2.15 Reliability of the Low-K Materials;391
11.2.2.16;8.2.2.16 Impact of Exotic Materials on Dual-Damascene Pattern Formation;394
11.2.2.17;8.2.2.17 Etching Processes and the Reliability;395
11.2.2.18;8.2.2.18 Reliability of Chemical-Mechanical Polishing (CMP);396
11.2.2.19;8.2.2.19 Cleaning Process and Reliability;397
11.2.3;8.2.3 Measurements;399
11.3;8.3 Summary;402
12;Glossary (Copper Interconnects);415
13;Index;425