Höfflinger CHIPS 2020 VOL. 2

New Vistas in Nanoelectronics
1. Auflage 2016
ISBN: 978-3-319-22093-2
Verlag: Springer Nature Switzerland
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 342 Seiten

Reihe: The Frontiers Collection

The release of this second volume of CHIPS 2020 coincides with the 50th anniversary of Moore's Law, a critical year marked by the end of the nanometer roadmap and by a significantly reduced annual rise in chip performance. At the same time, we are witnessing a data explosion in the Internet, which is consuming 40% more electrical power every year, leading to fears of a major blackout of the Internet by 2020.The messages of the first CHIPS 2020, published in 2012, concerned the realization of quantum steps for improving the energy efficiency of all chip functions. With this second volume, we review these messages and amplify upon the most promising directions: ultra-low-voltage electronics, nanoscale monolithic 3D integration, relevant-data, brain- and human-vision-inspired processing, and energy harvesting for chip autonomy. The team of authors, enlarged by more world leaders in low-power, monolithic 3D, video, and Silicon brains, presents new vistas in nanoelectronics, promising  Moore-like exponential growth sustainable through to the 2030s.

Autoren/Hrsg.

Höfflinger, Bernd

Inhaltsverzeichnis

1;Preface;6
2;Contents;8
3;Editor and Contributors;10
4;Authors’ Biography;13
5;Acronyms;22
6;Abstract;31
7;1 News on Eight Chip Technologies;32
7.1;Abstract;32
7.2;1.1 Overview;32
7.3;1.2 Bipolar-Transistor Technology;34
7.4;1.3 CMOS Integrated Circuits;35
7.5;1.4 Silicon-on-Insulator (SOI) CMOS Technology;39
7.6;1.5 3D CMOS Technologies;40
7.7;1.6 Ultra-Low-Voltage Differential Transmission-Gate CMOS Logic;41
7.8;1.7 Chip Stacks;47
7.9;1.8 Single-Electron-Transistor Technology;47
7.10;1.9 Conclusion;48
7.11;References;49
8;2 The Future of Low-Power Electronics;51
8.1;Abstract;51
8.2;2.1 Electronics Systems and Power-Efficiency;51
8.3;2.2 Low-Power CMOS Technology;55
8.3.1;2.2.1 Hybrid SOTB CMOS Technology;55
8.3.2;2.2.2 Low-Voltage SRAM;57
8.3.3;2.2.3 Low-Voltage Microprocessor and Logic Circuits;58
8.4;2.3 Low-Power Non-volatile Memories and Switches;61
8.4.1;2.3.1 MRAM for Cache Applications;63
8.4.2;2.3.2 Complementary Atom-Switch for Programmable Logic After Fabrication;65
8.4.3;2.3.3 SOTB-CMOS Microprocessor with Atom-Switch PROM;69
8.4.4;2.3.4 TRAM for Low-Power Storage;71
8.5;2.4 3D Integration;73
8.6;2.5 The Future of Low-Power Integrated Circuits;76
8.7;References;78
9;3 Monolithic 3D Integration;81
9.1;Abstract;81
9.2;3.1 Why Monolithic 3D;81
9.2.1;3.1.1 Lithography;83
9.2.2;3.1.2 On-Chip Interconnect;83
9.2.3;3.1.3 Transistor Variation;83
9.3;3.2 Historical Review of Monolithic 3D Technologies;86
9.3.1;3.2.1 Thin-Film Polysilicon-Based Monolithic 3D;86
9.3.2;3.2.2 Crystalline Overlay;86
9.3.3;3.2.3 Layer Transfer;87
9.3.4;3.2.4 Transistor Activation;88
9.3.4.1;3.2.4.1 The RCAT Process;88
9.3.4.2;3.2.4.2 The Gate Replacement Process;89
9.3.4.3;3.2.4.3 Laser-Annealing Process;91
9.4;3.3 Precision Bonders---A Game Changer for Monolithic 3D;91
9.4.1;3.3.1 Monolithic 3D IC Using Precision Bonders;92
9.4.2;3.3.2 Smart Alignment;93
9.4.3;3.3.3 Strata 2, 3---Examples;94
9.4.4;3.3.4 Monolithic 3D Cost Estimates;95
9.5;3.4 EDA for Monolithic 3D;96
9.6;3.5 Managing the Heat;98
9.7;3.6 3D Memories: 3D NAND,2026;100
9.7.1;3.6.1 Introduction to BiCS;100
9.7.2;3.6.2 3D-NAND;100
9.7.3;3.6.3 Making Contact Without Adding Lithography Steps;102
9.7.4;3.6.4 3D-NOR Flash;103
9.8;3.7 Advanced Work---Non-silicon Monolithic 3D;103
9.8.1;3.7.1 III--V Semiconductor 3D Integration;103
9.8.2;3.7.2 Monolithic 3D Integration of Semiconductor, Carbon Nano Tube, STT MRAM and RRAM;105
9.9;3.8 The Monolithic 3D Advantages;106
9.9.1;3.8.1 Introduction;106
9.9.2;3.8.2 Reduction in Die Size and Power;106
9.9.2.1;3.8.2.1 Reduction in Die Size;106
9.9.2.2;3.8.2.2 Reduction in Power;108
9.9.3;3.8.3 Significant Advantages for Using the Same Fab and Design Tools;108
9.9.3.1;3.8.3.1 Depreciation;108
9.9.3.2;3.8.3.2 Learning Curve---Yield;110
9.9.4;3.8.4 Heterogeneous Integration;110
9.9.4.1;3.8.4.1 Logic, Memory, I/O;110
9.9.4.2;3.8.4.2 Strata of Logic;112
9.9.4.3;3.8.4.3 Strata of Different Substrate Crystals and Fabrication Processes;113
9.9.5;3.8.5 Multiple Layers Processed Simultaneously---BiCS;113
9.9.6;3.8.6 Logic Redundancy Allowing 100x Integration with Good Yield;114
9.9.7;3.8.7 3D-FPGA;115
9.9.8;3.8.8 Modular Platform;116
9.9.9;3.8.9 Stacked Layers Are Naturally SOI;117
9.9.10;3.8.10 Local Interconnect Above and Below Transistor Layer;117
9.9.11;3.8.11 Re-buffering Global Interconnect by Upper Strata;117
9.9.12;3.8.12 Other Ideas;118
9.9.12.1;3.8.12.1 Image Sensor with Pixel Electronics;118
9.9.12.2;3.8.12.2 Micro-display;119
9.10;3.9 Conclusion;120
9.11;References;120
10;4 Analog-Digital Interfaces---Review and Current Trends;122
10.1;Abstract;122
10.2;4.1 Introduction;122
10.3;4.2 General ADC Performance Trends;123
10.4;4.3 Trends in Nyquist A/D Converters;128
10.4.1;4.3.1 SAR ADCs;130
10.4.2;4.3.2 Pipelined ADCs;130
10.4.3;4.3.3 Flash ADCs;130
10.4.4;4.3.4 Digitally Assisted Design;131
10.5;4.4 Trends in Delta-Sigma A/D Converters;131
10.5.1;4.4.1 Loop Filter;132
10.5.2;4.4.2 Quantizer;135
10.5.2.1;4.4.2.1 Voltage-Controlled Oscillator-Based Quantizer;135
10.5.2.2;4.4.2.2 Time-Encoding Quantizer;138
10.5.3;4.4.3 DAC;138
10.5.4;4.4.4 Conclusion on Delta-Sigma A/D Converters;139
10.6;4.5 Analog-to-Information Converters;139
10.7;4.6 Conclusions;141
10.8;References;141
11;5 Interconnects and Communication;146
11.1;Abstract;146
11.2;5.1 On-Chip and Chip-Chip Communication;146
11.3;5.2 Projections Wireline Communication;147
11.4;5.3 Wireless Communication;148
11.5;5.4 Optical Communication;150
11.6;5.5 Global Mobile Communication;150
11.7;5.6 Conclusion;151
11.8;References;152
12;6 Superprocessors;153
12.1;Abstract;153
12.2;6.1 Evolving Workloads;154
12.3;6.2 POWER8---a Big-Data Processor;155
12.4;6.3 Security;160
12.5;6.4 Optimization Across the Stack;162
12.6;6.5 Accelerators;164
12.7;6.6 Open Computing;167
12.8;6.7 Outlook;168
12.9;References;169
13;7 ITRS 2028---International Roadmap of Semiconductors;171
13.1;Abstract;171
13.2;7.1 General Observations;171
13.3;7.2 ORTC---Overall Roadmap Technology Characteristics;173
13.4;7.3 System Drivers;173
13.5;7.4 PIDS---Process Integration, Devices and Structures;174
13.6;7.5 ERD---Emerging Research Devices;174
13.7;7.6 Interconnects;175
13.8;7.7 RF-AMS: Radio-Frequency and Analog-Mixed-Signal Technologies;175
13.9;7.8 Conclusion;176
13.10;References;176
14;8 Nanolithographies;177
14.1;Abstract;177
14.2;8.1 The Progression of Optical Lithography;178
14.3;8.2 Extreme-Ultraviolet (EUV) Lithography;180
14.4;8.3 Multiple-Electron-Beam (MEB) Lithography;182
14.5;8.4 Comparison of Three Nanolithographies;187
14.6;8.5 2015 Perspective on 7 nm Lithography;190
14.7;References;190
15;9 News on Energy-Efficient Large-Scale Computing;192
15.1;Abstract;192
15.2;9.1 History and Background;192
15.3;9.2 Energy Efficiency;195
15.4;9.3 Conclusions;197
15.5;References;197
16;10 High-Performance Computing (HPC);198
16.1;Abstract;198
16.2;10.1 Highlights on Standard Processors;198
16.3;10.2 Special-Purpose Processors and Energy Efficiency;199
16.4;10.3 Supercomputers;201
16.5;10.4 Internet Servers;204
16.6;10.5 Conclusion;205
16.7;References;206
17;11 Memory;207
17.1;Abstract;207
17.2;11.1 Static Random-Access Memory (SRAM);208
17.3;11.2 The DRAM (Dynamic Random-Access Memory) at Its Final Stage;209
17.4;11.3 Breakthroughs in Non-volatile Memories (NV-RAM's);210
17.5;11.4 Conclusion;212
17.6;References;213
18;12 Intelligent Data Versus Big Data;214
18.1;Abstract;214
18.2;12.1 Progress in Nano-Chips Fosters Data Explosion;215
18.3;12.2 Intelligent Data from and for Our World;217
18.4;12.3 Digital Multipliers for Reality Data;223
18.5;12.4 Conclusion;224
18.6;References;225
19;13 HDR- and 3D-Vision Sensors;226
19.1;Abstract;226
19.2;13.1 Scaled CMOS Image Sensors;226
19.3;13.2 Hi-Speed Feature-Recognition Chips;227
19.4;13.3 High-Dynamic-Range HDR Video Sensors;228
19.5;13.4 HDRC Stereo Cameras;230
19.6;13.5 3D Time-of-Flight (TOF) Sensors;233
19.7;13.6 Conclusion;233
19.8;References;233
20;14 Perception-Inspired High Dynamic Range Video Coding and Compression;235
20.1;Abstract;235
20.2;14.1 Introduction;235
20.3;14.2 HDR Pixel Encoding;236
20.4;14.3 High Bit-Depth Compression;238
20.5;14.4 Backward-Compatible Compression;239
20.6;14.5 Perceptual Depth Compression for Stereoscopic Applications;240
20.7;14.6 Conclusion;242
20.8;References;243
21;15 MEMS---Micro-Electromechanical Sensors for the Internet of Everything;245
21.1;Abstract;245
21.2;15.1 Unique Growth of the MEMS Market;245
21.3;15.2 Automotive MEMS Applications and Scaling;247
21.4;15.3 Mobile Consumer Electronics;248
21.5;15.4 The ``Bosch'' Process;249
21.6;15.5 Sensors and Systems-Integration;250
21.7;15.6 MEMS-Enabled Systems and Their Consistent Development;251
21.8;15.7 Conclusion;253
21.9;Disclaimer;253
21.10;References;253
22;16 Networked Neural Systems;254
22.1;Abstract;254
22.2;16.1 Introduction;254
22.3;16.2 Health Monitor;255
22.3.1;16.2.1 PPG (Photo-Plethysmo-Graphical) Analysis;256
22.3.2;16.2.2 The Need for Modelling;257
22.4;16.3 Integrated Neural Systems;259
22.4.1;16.3.1 Synaptic Chips;259
22.4.2;16.3.2 Memristor;260
22.5;16.4 Distributed Neural Networks;261
22.5.1;16.4.1 Event-Directed Synchronization;261
22.5.2;16.4.2 Self-healing;262
22.6;16.5 Conclusion;263
22.7;References;264
23;17 Insertion of Retinal Implants in Worlwide Prostheses;266
23.1;Abstract;266
23.2;17.1 HDR Subretinal Implant Inspired by the Human Visual System;266
23.3;17.2 Chronicle of the Subretinal Implant;267
23.4;17.3 CE Certification and Results for Blind Patients Worldwide;268
23.5;17.4 Conclusion;270
23.6;References;271
24;18 Brain-Inspired Architectures for Nanoelectronics;272
24.1;Abstract;272
24.2;18.1 Introduction;273
24.3;18.2 Some Features of the Human Brain;274
24.4;18.3 Brain Simulation Approaches;278
24.5;18.4 Neurocomputers Based on Standard ICs;280
24.6;18.5 Neurocomputers Based on Neuro-ASICs;282
24.7;18.6 The Blue Brain Project;284
24.8;18.7 The SpiNNaker System;284
24.9;18.8 The SyNAPSE Program and the IBM TrueNorth Architecture;286
24.10;18.9 The BrainScaleS Wafer-Scale Neuromorphic Hardware System;288
24.11;18.10 Neurogrid;289
24.12;18.11 Comparison;291
24.13;18.12 Outlook;293
24.14;References;295
25;19 Energy-Harvesting Applications and Efficient Power Processing;298
25.1;Abstract;298
25.2;19.1 Systems and Applications;298
25.2.1;19.1.1 Wearable Devices;298
25.2.2;19.1.2 Condition Monitoring;299
25.3;19.2 Circuit Components for Energy Harvesting Applications;302
25.3.1;19.2.1 AC Sources;303
25.3.1.1;19.2.1.1 Wireless Power Transmission Circuits;303
25.3.1.2;19.2.1.2 Interfaces for Vibration-Based Kinetic Energy Harvesting;305
25.3.2;19.2.2 DC Sources;310
25.3.2.1;19.2.2.1 Micro Fuel Cells;310
25.3.2.2;19.2.2.2 Interface Circuits for Thermoelectric Generators;311
25.3.2.3;19.2.2.3 Interface Circuits for Solar Cells;313
25.3.3;19.2.3 Ultra-Low-Voltage Control Circuits;316
25.3.3.1;19.2.3.1 Analog;316
25.3.3.2;19.2.3.2 Digital;317
25.4;19.3 Conclusion;318
25.5;References;319
26;20 2020 and Beyond;324
26.1;Abstract;324
26.2;20.1 Chip Market Forecasts for 2020;324
26.3;20.2 The Electric-Power Singularity of 2020;325
26.4;20.3 Monolithic and Heterogeneous 3D Integration;326
26.5;20.4 Low-Voltage, New Digital Computing;327
26.6;20.5 New Video;328
26.7;20.6 Reliable Intelligent-Learning Nano-Systems;328
26.8;20.7 The Era of Energy-Autonomous Nano-Chip Systems;328
26.9;20.8 Another Singularity?;329
26.10;References;330
27;Titles in this Series;332
28;Index;336