Holdsworth Digital Logic Design

2. Auflage 2014
ISBN: 978-1-4831-4222-7
Verlag: Elsevier Science & Techn.
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 462 Seiten, Web PDF

Digital Logic Design, Second Edition provides a basic understanding of digital logic design with emphasis on the two alternative methods of design available to the digital engineer. This book describes the digital design techniques, which have become increasingly important. Organized into 14 chapters, this edition begins with an overview of the essential laws of Boolean algebra, K-map plotting techniques, as well as the simplification of Boolean functions. This text then presents the properties and develops the characteristic equations of a number of various types of flip-flop. Other chapters consider the design of synchronous and asynchronous counters using either discrete flip-flops or shift registers. This book discusses as well the design and implementation of event driven logic circuits using the NAND sequential equation. The final chapter deals with simple coding techniques and the principles of error detection and correction. This book is a valuable resource for undergraduate students, digital engineers, and scientists.

Autoren/Hrsg.

Holdsworth, B.

Inhaltsverzeichnis

1;Front Cover;1
2;Digital Logic Design;4
3;Copyright Page;5
4;Table of Contents;10
5;Dedication
;3
6;Preface to the Second Edition;6
7;Preface to the First Edition;7
8;Chapter 1.
Boolean algebra;16
8.1;1.1 Introduction;16
8.2;1.2 The logic of a switch;17
8.3;1.3 The AND function;17
8.4;1.4 The OR function;19
8.5;1.5 The inversion function;20
8.6;1.7 The idempotency theorem;22
8.7;1.8 The theorems of union and intersection;23
8.8;1.9 The redundancy or absorption theorem;24
8.9;1.10 The determination of the complementary function;25
8.10;1.11 Theorems on commutation, association and distribution;27
8.11;1.12 The consensus theorem;28
8.12;Problems;29
9;Chapter 2. Karnaugh maps and function simplification;31
9.1;2.1 Introduction;31
9.2;2.2 Product and sum terms;31
9.3;2.3 Canonical forms;33
9.4;2.4 Boolean functions of two variables;33
9.5;2.5 The Karnaugh map;35
9.6;2.6 Plotting Boolean functions on a Karnaugh map;37
9.7;2.7 Simplification of Boolean functions;40
9.8;2.8 The inverse function;42
9.9;2.9 'Don't care' terms;43
9.10;2.10 The plotting and simplification of P-of-S expressions;45
9.11;2.11 The Quine-McCluskey tabular simplification method;47
9.12;2.12 Properties of prime implicant tables;52
9.13;2.13 Cyclic prime implicant tables;53
9.14;2.14 Semi-cyclic prime implicant tables;56
9.15;2.15 Simplification of functions containing 'can't happen' term;57
9.16;2.16 The decimal approach to Quine-McCluskey;57
9.17;Problems;61
10;Chapter 3.
NAND and NOR logic;64
10.1;3.1 Introduction;64
10.2;3.2 The NAND function;64
10.3;3.3 The implementation of AND and OR functions using NAND gates;66
10.4;3.4 The implementation of S-of-P expressions using NAND gates;67
10.5;3.5 The NOR function;70
10.6;3.6 The implementation of OR and AND functions using NOR gates;71
10.7;3.7 The implementation of P-of-S expressions using NOR gates;72
10.8;3.8 The implementation of S-of-P expressions using NOR gates;72
10.9;3.9 Gate expansion;74
10.10;3.10 Miscellaneous gates;75
10.11;3.11 The tri-state gate;78
10.12;3.12 The exclusive-OR gate;78
10.13;Problems;83
11;Chapter 4.
Combinational logic design;85
11.1;4.1 Introduction;85
11.2;4.2 The half-adder;86
11.3;4.3 The full adder;87
11.4;4.4 The full subtracter;89
11.5;4.5 Comparators;91
11.6;4.6 Parity generation and checking;92
11.7;4.7 Code conversion;97
11.8;4.8 Binary to Gray code converter;99
11.9;4.9 Interrupt sorters;102
11.10;Problems;104
12;Chapter 5.
Single-bit memory elements;106
12.1;5.1 Introduction;106
12.2;5.2 The T flip-flop;106
12.3;5.3 The SR flip-flop;110
12.4;5.4 The JK flip-flop;114
12.5;5.5 The D flip-flop;119
12.6;5.6 The edge-triggered flip-flop;121
12.7;5.7 The latching action of a flip-flop;123
12.8;Problems;125
13;Chapter 6.
Counters;128
13.1;6.1 Introduction;128
13.2;6.2 Scale-of-two up-counter;128
13.3;6.3 Scale-of-four up-counter;130
13.4;6.4 Scaleof-eight up-counter;130
13.5;6.5 Scale-of 2N up-counter;131
13.6;6.6 Series and parallel connection of counters;132
13.7;6.7 Synchronous down-counters;133
13.8;6.8 Scale-of five up-counter;133
13.9;6.9 Decade binary up-counter;137
13.10;6.10 Decade binary down-counter;140
13.11;6.11 Decade Gray code 'up' counter;140
13.12;6.12 Scale-of-16 up/down counter;145
13.13;6.13 Asynchronous binary counters;146
13.14;6.14 Scale-often asynchronous up-counter;149
13.15;6.15 Asynchronous resettable counters;150
13.16;6.16 Integrated-circuit counters;151
13.17;6.17 Cascading of IC counter chips;154
13.18;Problems;155
14;Chapter 7. Shift register counters and generators;158
14.1;7.1 Introduction;158
14.2;7.2 The four-bit shift register with parallel loading;159
14.3;7.3 The four-bit shift-left, shift-right register;159
14.4;7.4 The use of shift registers as counters;160
14.5;7.5 The universal state diagram for shift registers;162
14.6;7.6 The design of a decade counter;164
14.7;7.7 Shift register sequence generators;167
14.8;7.8 The ring counter;170
14.9;7.9 The twisted ring or Johnson counter;174
14.10;7.10 Shift registers with exclusive-OR feedback;177
14.11;Problems;183
15;Chapter 8.
Clock-driven sequential circuits;185
15.1;8.1 Introduction;185
15.2;8.2 Analysis of a clocked sequential circuit;185
15.3;8.3 The design procedure for clocked sequential circuits;190
15.4;8.4 The design of a sequence generator;198
15.5;8.5 Moore and Mealy state machines;201
15.6;8.6 Pulsed synchronous circuits;205
15.7;8.7 State reduction;208
15.8;8.8 State assignment;213
15.9;Problems;218
16;Chapter 9.
Event-driven circuits;223
16.1;9.1 Introduction;223
16.2;9.2 The museum problem;223
16.3;9.3 Races and cycles;227
16.4;9.4 Race-free assignment for a three-state machine;230
16.5;9.5 The pump problem;231
16.6;9.6 Race-free assignment for a four-state machine;234
16.7;9.7 A sequence detector;237
16.8;Problems;243
17;Chapter 10.
Digital design with MSI;248
17.1;10.1 Introduction;248
17.2;10.2 Data selector or multiplexer;249
17.3;10.3 The multiplexer as a logic function generator;250
17.4;10.4 Decoders and demultiplexers;259
17.5;10.5 Decoder applications;260
17.6;10.6 Read-only memories (ROMs);265
17.7;10.7 Addressing techniques for ROMs;267
17.8;10.8 Design of sequential circuits using ROMs;269
17.9;10.9 Programmable logic arrays (PLAs);274
17.10;10.10 Design of sequential circuits using PLA s;277
17.11;Problems;280
18;Chapter 11.
Arithmetic circuits;285
18.1;11.1 Introduction;285
18.2;11.2 The four-bit parallel adder;285
18.3;11.3 The carry look-ahead adder;286
18.4;11.4 Complement arithmetic;290
18.5;11.5 The 2's complement;291
18.6;11.6 The 1's complement;291
18.7;11.7 Representation of binary numbers in a digital machine;292
18.8;11.8 Addition and subtraction using 2's complement arithmetic;293
18.9;11.9 Addition and subtraction using 1's complement arithmetic;294
18.10;11.10 Overflow;295
18.11;11.11 Serial addition and subtraction;297
18.12;11.12 Decimal arithmetic with MSI adders;298
18.13;11.13 The use of complement arithmetic for decimal operations;301
18.14;11.14 Adder/subtractor for decimal arithmetic;304
18.15;11.15 Arithmetic/logic unit;306
18.16;11.16 Design of an arithmetic/logic unit;307
18.17;11.17 Combinational binary multipliers;311
18.18;11.18 ROM implemented binary multipliers;314
18.19;11.19 The shift and add multiplier;317
18.20;11.20 Binary division;321
18.21;Problems;325
19;Chapter 12.
Hazards;329
19.1;12.1 Introduction;329
19.2;12.2 Gate delays;329
19.3;12.3 The generation of spikes;330
19.4;12.4 The production of static hazards in combinational networks;332
19.5;12.5 The elimination of static hazards;334
19.6;12.6 Design of hazard-free combinational network«;337
19.7;12.7 Detection of hazards in an existing network;340
19.8;12.8 Hazard-free asynchronous circuit design;342
19.9;12.9 Dynamic hazards;345
19.10;12.10 Essential hazards;347
19.11;Problems;349
20;Chapter 13. Fault diagnosis in combinational circuits;351
20.1;13.1 Introduction;351
20.2;13.2 Fault detection and location;352
20.3;13.3 A fault test for a 2-input AND gate;354
20.4;13.4 The fault detection table;355
20.5;13.5 The fault location table;361
20.6;13.6 Adaptive testing;362
20.7;13.7 Path sensitisation;365
20.8;13.8 Path sensitisation applied to combinational networks;367
20.9;13.9 Path sensitisation in networks with fanout;370
20.10;13.10 Two-level circuit fault detection in AND/OR circuit;374
20.11;13.11 Two-level circuit fault detection in OR/AND circuits;378
20.12;13.12 Tabulation method of fault diagnosis for two-level circuits;382
20.13;13.13 Fault detection in multi-level circuits;385
20.14;13.14 Boolean difference;388
20.15;13.15 The chain tuie;392
20.16;Problems;396
21;Chapter 14.
Coding systems for error control;400
21.1;14.1 Introduction;400
21.2;14.2 Definition of a code;401
21.3;14.3 Information content of the decimal and hexadecimal numbersystems;401
21.4;14.4 Coding theory terminology;402
21.5;14.5 The conditions for error detection;403
21.6;14.6 The Boolean Circle and the correction domain;405
21.7;14.7 The transmission equation;406
21.8;14.8 The undetected error rate;407
21.9;14.9 Linear block codes;409
21.10;14.10 Backward error correction (BEC);410
21.11;14.11 Matrix representation of linear block codes;414
21.12;14.12 Decoding the received word;418
21.13;14.13 Forward error correction;420
21.14;Problems;423
22;Answers to problems;425
23;Bibliography;456
24;Index;458