Holdsworth Microprocessor Engineering

1. Auflage 2013
ISBN: 978-1-4831-0490-4
Verlag: Elsevier Science & Techn.
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 352 Seiten, Web PDF

Microprocessor Engineering provides an insight in the structures and operating techniques of a small computer. The book is comprised of 10 chapters that deal with the various aspects of computing. The first two chapters tackle the basic arithmetic and logic processes. The third chapter covers the various memory devices, both ROM and RWM. Next, the book deals with the general architecture of microprocessor. The succeeding three chapters discuss the software aspects of machine operation, while the last remaining three chapters talk about the relationship of the microprocessor with the outside world. The text will be of great use to undergraduate students of various disciplines. Practitioners of computer-related fields with no previous digital experience will find this book useful.

Autoren/Hrsg.

Holdsworth, B.

Inhaltsverzeichnis

1;Front Cover;1
2;Microprocessor Engineering;2
3;Copyright Page;3
4;Preface;4
5;Table of Contents;8
6;Chapter 1. Arithmetic;14
6.1;1.1 Introduction;14
6.2;1.2 Number systems;15
6.3;1.3 Conversion between number systems;16
6.4;1.4 Representation of numerical data in a machine;19
6.5;1.5 Unsigned arithmetic;19
6.6;1.6 Signed arithmetic;24
6.7;1.7 Complement arithmetic;24
6.8;1.8 Addition and subtraction of 2's complement numbers;27
6.9;1.9 Multiplication of 2's complement numbers;29
6.10;1.10 Division of 2's complement numbers;30
6.11;1.11 Binary coded decimal arithmetic;32
6.12;1.12 10's complement arithmetic;34
6.13;1.13 Signed BCD arithmetic;35
6.14;1.14 Multiplication and division of BCD numbers;35
6.15;1.15 Decimal to binary conversion;36
6.16;1.16 Fractional binary numbers;37
6.17;Problems;39
7;Chapter 2. Logic;42
7.1;2.1 Introduction;42
7.2;2.2 Gates;42
7.3;2.3 Inverters;43
7.4;2.4 Alternative logic representations;44
7.5;2.5 The tri-state gate;46
7.6;2.6 The D-type flip-flop;48
7.7;2.7 The edge-triggered D-type flip-flop;49
7.8;2.8 The level-triggered D-type flip-flop;50
7.9;2.9 Asynchronous controls;51
7.10;2.10 Flip-flop conversion;51
7.11;2.11 Flip-flop operating characteristics;52
7.12;2.12 Registers;53
7.13;2.13 Data transfer operations;54
7.14;2.14 The data latching register;56
7.15;2.15 The tri-state register;57
7.16;2.16 The edge-triggered register;58
7.17;2.17 Data selectors or multiplexers;58
7.18;2.18 Demultiplexers and decoders;59
7.19;2.19 Encoders;62
7.20;2.20 Parity generation and checking;64
7.21;2.21 Comparators;67
7.22;2.22 Arithmetic circuits;68
7.23;2.23 Arithmetic/logic unit;72
7.24;Problems;74
8;Chapter 3. Memory;77
8.1;3.1 Introduction;77
8.2;3.2 The register representation of memory;78
8.3;3.3 Memory timing;79
8.4;3.4 Memory classification;80
8.5;3.5 ROMs;82
8.6;3.6 PROMs;84
8.7;3.7 EPROMs;85
8.8;3.8 RWMs;85
8.9;3.9 Static MOS RWM;87
8.10;3.10 The dynamic RWM;88
8.11;3.11 The bipolar RWM;89
8.12;3.12 Memory expansion;90
8.13;3.13 Memory address decoding;92
8.14;3.14 Absolute addressing;93
8.15;3.15 Memory pages;98
8.16;Problems;99
9;Chapter 4. Small computer architecture;101
9.1;4.1 Introduction;101
9.2;4.2 The block diagram of a microcomputer system;101
9.3;4.3 The bus system;103
9.4;4.4 Microprocessor architecture;104
9.5;4.5 Internal registers;105
9.6;4.6 The arithmetic/logic unit;109
9.7;4.7 Basic microprocessor operation;110
9.8;4.8 The 8085A microprocessor;112
9.9;4.9 The architecture of the 8085A;115
9.10;4.10 The operation of the 8085A;115
9.11;4.11 State and timing diagrams for the 8085A;119
9.12;4.12 The WAIT state;121
9.13;4.13 The HALT state;124
9.14;4.14 The SDK 85 expandable microcomputing kit;125
9.15;4.15 Other microprocessors;128
9.16;4.16 The Intel 8080A;128
9.17;4.17 The Zilog Z80;133
9.18;4.18 The Motorola 6800;136
9.19;Problems;138
10;Chapter 5. The instruction set I: data transfer, arithmetic and logic operations;140
10.1;5.1 Introduction;140
10.2;5.2 Machine code representation of instructions;141
10.3;5.3 Mnemonic representation of instructions;142
10.4;5.4 Addressing modes;145
10.5;5.5 Implied addressing;146
10.6;5.6 Immediate addressing;146
10.7;5.7 Direct addressing;147
10.8;5.8 Register and register indirect addressing;148
10.9;5.9 Indexed addressing;150
10.10;5.10 Relative addressing;151
10.11;5.11 Modified page zero addressing;152
10.12;5.12 Instruction groupings for the 8085A;153
10.13;5.13 Data transfer instructions;153
10.14;5.14 Transfers employing immediate addressing;153
10.15;5.15 Inter-register transfers;155
10.16;5.16 Transfers using the direct addressing mode;157
10.17;5.17 Transfers using the indirect addressing mode;158
10.18;5.18 The input and output instructions;160
10.19;5.19 Arithmetic and logic operations;160
10.20;5.20 Immediate arithmetic and logic instructions;161
10.21;5.21 Register arithmetic and logic instructions;167
10.22;5.22 Indirect register arithmetic and logic instructions;170
10.23;5.23 Rotate and data shift instructions;171
10.24;5.24 Miscellaneous instructions;174
10.25;Problems;176
11;Chapter 6. The instruction set II: jump, call, return and stack control;178
11.1;6.1 Introduction;178
11.2;6.2 Flowcharts;179
11.3;6.3 Basic flowchart combinations;181
11.4;6.4 The JUMP instructions;184
11.5;6.5 The program implementation of the IF-THEN/ELSE structure;186
11.6;6.6 Program loops;187
11.7;6.7 A program implementation of the SELECT structure;190
11.8;6.8 Stack operations and instructions;191
11.9;6.9 Subroutines;195
11.10;6.10 The call and return instructions;198
11.11;Problems;200
12;Chapter 7. Assembly language programming and software aids;202
12.1;7.1 Introduction;202
12.2;7.2 Source and object programs;203
12.3;7.3 The fields of an assembly language statement;203
12.4;7.4 Manual assembly;205
12.5;7.5 Assembler directives;207
12.6;7.6 The two-pass assembler;211
12.7;7.7 Program execution time;214
12.8;7.8 Software generation of time delays;216
12.9;7.9 Generation of a repetitive waveform using software delays;217
12.10;7.10 Subroutine linkage;218
12.11;7.11 Re-entrancy;221
12.12;7.12 Macros;222
12.13;7.13 High level languages;224
12.14;7.14 Compilers;226
12.15;7.15 Interpreters;226
12.16;7.16 Monitors and operating systems;227
12.17;7.17 Program libraries;230
12.18;Problems;231
13;Chapter 8. Program controlled input/output data transfers;232
13.1;8.1 Introduction;232
13.2;8.2 I/O interfacing;233
13.3;8.3 Isolated and memory mapped I/O;234
13.4;8.4 The input/output instructions for the 8085A;238
13.5;8.5 The timing diagram for an isolated I/O operation in the 8085A;238
13.6;8.6 Design of peripheral selection logic;239
13.7;8.7 Memory mapped I/O operations;243
13.8;8.8 Port selection in a memory mapped system;244
13.9;8.9 Assembly language instructions for memory mapped I/O devices;245
13.10;8.10 Transfer of parallel data under program control;246
13.11;8.11 Polling;249
13.12;8.12 Peripheral interface chips;252
13.13;8.13 Multi-function LSI devices;256
13.14;8.14 Serial transfer of data;258
13.15;8.15 Asynchronous serial data transfer;259
13.16;8.16 Synchronous serial data transfer;261
13.17;8.17 Protocol;263
13.18;8.18 The universal asynchronous receiver/transmitter (UART);265
13.19;8.19 Communication techniques with long transmission channels;267
13.20;8.20 The serial I/O pins of the 8085A processor;270
13.21;Problems;272
14;Chapter 9. Interrupts;274
14.1;9.1 Introduction;274
14.2;9.2 The interrupt process;274
14.3;9.3 Maskable and non-maskable interrupts;275
14.4;9.4 The salient features of an interrupt system;276
14.5;9.5 Examination of the interrupt line;277
14.6;9.6 Transfer of control to the interrupt service routine;277
14.7;9.7 Preservation and restoration of status;278
14.8;9.8 Identifying the interrupt source;279
14.9;9.9 Software polling;280
14.10;9.10 Vectored interrupts;281
14.11;9.11 Hardware polling for interrupt identification;282
14.12;9.12 A priority interrupt system;283
14.13;9.13 Enabling and disabling interrupts;285
14.14;9.14 The 8085A interrupts;286
14.15;9.15 State diagram for the 8085A, including interrupt logic;288
14.16;9.16 Interrupt response of the 8085A;289
14.17;9.17 The 6800 interrupt structure;291
14.18;9.18 Direct memory access (DMA);294
14.19;9.19 The HOLD state;296
14.20;9.20 Basic requirements of a DMA transfer;297
14.21;9.21 Basic requirements of a DMA controller;298
14.22;9.22 DMA with multiple external devices;299
14.23;9.23 The Intel 8257 DMA controller;299
14.24;Problems;301
15;Chapter 10. Data conversion;303
15.1;10.1 Introduction;303
15.2;10.2 Basic principles of digital-to-analogue conversion;303
15.3;10.3 The weighted resistor DAC;306
15.4;10.4 The use of R/2R ladder network in DACs;308
15.5;10.5 Multiplying D/A converters;309
15.6;10.6 Current switching DACs;311
15.7;10.7 Converter coding;312
15.8;10.8 Analogue polarity;314
15.9;10.9 Resolution;315
15.10;10.10 Errors in D/A converters;316
15.11;10.11 Settling time;318
15.12;10.12 Interfacing a DAC to a source of digital data;319
15.13;10.13 The principles of analogue-to-digital conversion;321
15.14;10.14 Sample and hold circuits;323
15.15;10.15 Comparators;326
15.16;10.16 Counting ADCs;327
15.17;10.17 Principle of successive approximation conversion;329
15.18;10.18 Successive approximation ADC;331
15.19;10.19 Parallel A/D conversion;333
15.20;10.20 Errors in analogue-to-digital converters;335
15.21;10.21 Software implementation of ADCs;336
15.22;Problems;337
16;Appendix: Intel 8085A Instruction set summary;340
17;Bibliography;346
18;Index;348