Spacer Engineered FinFET Architectures

High-Performance Digital Circuit Applications
1. Auflage 2017
ISBN: 978-1-4987-8359-0
Verlag: Taylor & Francis Inc

Buch, Englisch, 154 Seiten, Format (B × H): 241 mm x 161 mm, Gewicht: 384 g

This book focusses on the spacer engineering aspects of novel MOS-based device–circuit co-design in sub-20nm technology node, its process complexity, variability, and reliability issues. It comprehensively explores the FinFET/tri-gate architectures with their circuit/SRAM suitability and tolerance to random statistical variations.

Autoren/Hrsg.

Kaushik, Brajesh Kumar

Dasgupta, Sudeb

Pal, Pankaj Kumar

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise
• Technische Wissenschaften Energietechnik | Elektrotechnik Elektrotechnik

Inhaltsverzeichnis

Introduction to Nanoelectronics. Tri-gate FinFET Technology and Its Advancement. Dual-k Spacer Device Architecture and Its Electrostatics. Capacitive Analysis and Dual-k based Digital Circuit Design. Design Metric Improvement of Dual-k based SRAM Cell. Statistical Variability and Sensitivity Analysis.

Über Autor(innen)

Sudeb Dasgupta, Brajesh Kumar Kaushik, Pankaj Kumar Pal