Kirischian Reconfigurable Computing Systems Engineering

Virtualization of Computing Architecture
Erscheinungsjahr 2015
ISBN: 978-1-4822-8224-5
Verlag: Taylor & Francis
Format: PDF
Kopierschutz: Adobe DRM (»Systemvoraussetzungen)

E-Book, Englisch, 346 Seiten

This book offers a complete road map to the architectural synthesis of reconfigurable computing systems (RCS), exploring the process from both the system and the on-chip level. It describes in detail the hardware design of RCS platforms—from components to schematic diagrams and printed circuit board layouts—for application-specific workloads, presenting original methodology for rapid multi-parametric optimization. Featuring illustrative examples, case studies, homework problems, and references to important literature, the text provides a solid understanding of RCS technology and the areas where it’s most effective.

Autoren/Hrsg.

Kirischian, Lev

Fachgebiete

• Mathematik | Informatik EDV | Informatik Technische Informatik

Inhaltsverzeichnis

Introduction to RCS

Introduction

Definition of Computing Architecture

Correspondence between a Task and Computing Architecture

Processors with Programmable Procedure

Processors with Programmable Architecture

Definition of Reconfigurable Computing Systems - RCS

Major Components of RCS and Their Hardware Basis

Advantages of RCS and Areas of Application

Summary

Problems and Exercises

References

RCS System Organization

RCS Architecture Organization

Introduction

Classification of RCS Architectures

Statically and Dynamically Reconfigurable RCS

Homogenous and Heterogeneous RCS Architectures

Fine-Grain and Coarse-Grain RCS Architectures

Statically Reconfigurable RCS Architectures

RCS for Rapid Prototyping of Application Specific Processors (ASP)

RCS with Remotely Reconfigurable Architecture

RCS for Multi-Mode Applications

Dynamically (Run-Time) Reconfigurable RCS Architectures

Concept of Spatial and Temporal Partitioning of RCS Resources

RCS with Run-Time Spatially Reconfigurable Architecture

RCS with Run-Time Temporally Reconfigurable Architecture

Summary

Problems and Exercises

References

RCS Hardware Components

Introduction

Major Hardware Components of RCS Architecture

Reconfigurable Field of Computing Resources

Reconfigurable Memory Resources

Reconfigurable Interface Resources

Configuration Controllers

Configuration Memory Hierarchy

Configuration Bus and Interface

Hardware Basis for RCS

Concept of Programmable Logic Devices

Configurable Logic Blocks with Switching Logic Elements

Look-Up-Table (LUT)-Based Configurable Logic Blocks

Routing Elements and Routing Programming

Complex Programmable Gate Array Devices (CPLD)

Field Programmable Gate Array (FPGA) Devices

Fine-Grain Homogenous FPGA Organization

Coarse-Grain Components in Modem FPGA

FPGA with Run-Time Partial Reconfiguration

Coarse Grained Reconfigurable Array (CGRA) Devices

Field Programmable Object Array (FPOA) Devices

Summary

Problems and Exercises

References

IP-Cores, Virtual Components, and Virtual Processors

Introduction

Languages and CAD Systems for RCS Development

Concept of HDL: Hardware Description Languages

Main HDL: VHDL and Verilog

Intellectual Property (IP)-Cores

Virtual Hardware Components - VHCs

Concept of Macro-Operator (MO) and VHC

Concept of Application Specific Virtual Processor - ASVP

Task Segmentation and Concept of Segment Specific Virtual Processor - SSVP

Summary

Problems and Exercises

References

RCS Development and Architecture Virtualization

High-Level Synthesis Stage

Introduction

Classification of the Workload and Workload Analysis

System Specification Analysis: Functional and Technical Specifications

High-Level Synthesis of RCS Architecture: System Level and On-Chip Level Architecture

Component Set Determination and Partitioning on Hardware and Software Components

Virtualization of Components and Creation of Component Integration Procedures

Architectural Support of RCS with Temporally Partitioned Reconfigurable Resources

Architectural Support of RCS with Spatially Portioned Reconfigurable Resources

Summary

Problems and Exercises

References

Architecture Optimization Process

Introduction

Analysis of Cost-Efficiency and Multi-Parametric Optimization of RCS Architecture

Representation of the Design Space of RCS Architecture

Concept of ACG: Architecture Configuration Graph

Mono-Parametric Arrangement of ACG: Local and Hierarchical ACG Arrangement

Selection of "Border" Variant of Architecture on Partially Arranged ACG

Multi-Parametric Optimization Process and Determination of Pareto-Optimal Set of Architecture Variants

Summary

Problems and Exercises

References

High-Level Synthesis of Virtual Hardware Components

Introduction

Analysis of Function: Determination of Algorithm and Data Structure

Algorithm Representation in a Form of Sequencing Graph (SG)

Scheduling Of Sequencing Graph and Resource Binding

Constraint Analysis and Optimization Requirements

Creation of the VHC "Symbol"

Determination of the Data-Path on the Base of Scheduled SG

Determination of Multiplexing Scheme for Primitive Resources and Conversion of Scheduled and Binded SG to the Data-Path Block Diagram

Determination of the Control Procedure

Determination of Interfaces and Synchronization

Integration of VHC Data-Path with Interfaces and Control Unit and Creation of Complete Block Diagram of the VHC

Summary

Problems and Exercises

References

Optimization of Virtual Hardware Component's Architecture

Introduction

Analysis of Resources Required For VHC and Creation of ACG

Creation of Performance Evaluation Models for Each Constrained Parameter

Analysis of Mini-Max Variants of Architecture for the VHC

Analysis of Critical Variants of VHC and ACG Hierarchical Arrangement

Selection of Border Variant for the Performance Parameter

Determination of the Pareto-Optimal Set of VHC Variants

Selection the Optimal Variant of VHC Architecture

Case Study

Summary

Problems and Exercises

References

Synthesis of RCS Architecture with Temporal Partitioning Mechanism

Introduction

Analysis of Application and Algorithm Representation in Terms of Macro-Operators

Segmentation of Application Sequencing Graph

Synthesis of Segment Specific Processor (SSP) On the Base of VHCs

Creation of the Set of SSPs for the Application and Execution Schedule(s)

Selection of the Reconfigurable Component Base for the RCS

Determination and Design of Interface Component of the RCS

Organization of Data-Memory Hierarchy

Organization of the Configuration Memory Hierarchy

Organization of Reconfiguration Sub-System of the RCS

Determination of Clock and Power Distribution Components of the RCS

Integration of Components into the Complete RCS Architecture Block Diagram

Case Study: MARS Platform

Summary

Problems and Exercises

References

Synthesis of RCS Architecture with Spatial Partitioning Mechanism

Introduction

Analysis of Application and Determination of Static and Variable Segments

Synthesis of the Static (Skeleton) Component of the On-Chip Architecture

Selection of the Set of VHCs for Application Specific Virtual Processors (ASVP)

Synthesis of the Set of ASVPs for All Variations (Modes) of an Application

Selection of the Reconfigurable Component Base for the RCS

Determination and Design of Interface Component of the RCS

Organization of Data-Memory Hierarchy

Organization of the Configuration Memory Hierarchy

Organization of Reconfiguration Sub-System of the RCS

Determination of Clock and Power Distribution Components of the RCS

Integration of Components into the Complete RCS Architecture Block Diagram

Case Study: MARS Platform

Summary

Problems and Exercises

References

RCS Implementation, Prototyping, and Verification

RSC Design and Implementation

Introduction

VHC Design: From Symbol and Block Diagram to HDL-Code

VHC Compilation and Verification

ASVP/SSP Compilation and Verification

RCS Hardware Design

From Platform Block Diagram to Schematic Capture Design

Printed Circuit Board (PCB) Layout and Design

RCS Platform Prototyping and Test

RCS Platform Integration with Virtual Hardware Components and Processors

SSP Integration in Temporal Domain According to Schedule(s)

ASVP Integration in Spatial Domain According to Modes of Operation

RCS Platform Integration with Peripherals, Data Sources, and Instruments

Creation of the RCS Verification Environment and Test-Procedures

RSC Verification Process

Technical Documentation Structure and Final Technical Report

Summary

Problems and Exercises

References

Case Studies of the Dynamically Reconfigurable RCS Development

Introduction

AGORA: Adaptive Group Organized Reconfigurable Architecture

RCS Platform Architecture for Multi Video-Stream Processing Applications

Spatial Partitioning Mechanism for ASVP for Xilinx Virtex-IIPro FPGA

Platform Design, Implementation, and Test Environment

MARS: Multi-Mode Adaptive Reconfigurable System

RCS Platform Architecture for Multi-Mode Stream Processing Applications

Spatial Partitioning Mechanism for Xilinx Virtex-4LX FPGA

Temporal Partitioning Mechanism for Xilinx Virtex-4LX FPGA

Platform Design, Implementation and Test Environment

Summary

References

Appendices