McLaurin / Waayers The Core Test Wrapper Handbook

Rationale and Application of IEEE Std. 1500™
1. Auflage 2006
ISBN: 978-0-387-34609-0
Verlag: Springer-Verlag
Format: PDF
Kopierschutz: Adobe DRM (»Systemvoraussetzungen)

E-Book, Englisch, 276 Seiten

In the early to mid-1990's while working at what was then Motorola Se- conductor, business changes forced my multi-hundred dollar microprocessor to become a tens-of-dollars embedded core. I ran into first hand the problem of trying to deliver what used to be a whole chip with something on the order of over 400 interconnect signals to a design team that was going to stuff it into a package with less than 220 signal pins and surround it with other logic. I also ran into the problem of delivering microprocessor specification verifi- tion – a microprocessor is not just about the functions and instructions included with the instruction set, but also the MIPs rating at some given f- quency. I faced two dilemmas: one, I could not deliver functional vectors without significant development of off-core logic to deal with the reduced chip I/O map (and everybody's I/O map was going to be a little different); and two, the JTAG (1149. 1) boundary scan ring that was around my core when it was a chip was going to be woefully inadequate since it did not support - speed signal application and capture and independent use separate from my core. I considered the problem at length and came up with my own solution that was predominantly a separate non-JTAG scan test wrapper that supported at-speed application of launch-capture cycles using the system clock. But my problems weren't over at that point either.

Autoren/Hrsg.

McLaurin, Teresa

Waayers, Tom

Inhaltsverzeichnis

1;Contents;8
2;List of Figures;16
3;List of Tables;22
4;Foreword;24
5;Preface;28
6;Acknowledgements;30
7;Introduction;31
8;Chapter 1 What is the IEEE 1500 Standard?;33
8.1;1.1 The IEEE 1500 Wrapper Architecture;36
8.1.1;1.1.1 The Wrapper Interface Port;37
8.1.2;1.1.2 The 1500 Wrapper Instruction Register;38
8.1.3;1.1.3 The Wrapper Boundary Register;38
8.1.4;1.1.4 The Wrapper Bypass Register;39
8.2;1.2 Compliance to IEEE 1500;39
8.2.1;1.2.1 IEEE 1500 Unwrapped Compliance;39
8.2.2;1.2.2 IEEE 1500 Wrapped Compliance;40
8.3;1.3 The Core Test Language (CTL);41
8.3.1;1.3.1 What is CTL?;41
9;Chapter 2 Why use the IEEE 1500 Standard?;43
9.1;2.1 Introduction;43
9.1.1;2.1.1 Test Reuse and Partitioning;43
9.1.2;2.1.2 Partition-Based Testing, Debug and Diagnosis;47
9.2;2.2 Why Was a Standard Needed?;48
10;Chapter 3 Illustration Example;51
10.1;3.1 Introduction;51
10.2;3.2 Unwrapped Core;51
10.3;3.3 Writing CTL For the EX Core;55
10.3.1;3.3.1 CTL Code Convention;55
10.3.2;3.3.2 CTL Code For the Unwrapped EX Core;55
11;Chapter 4 Design of the IEEE 1500 Interface Port;59
11.1;4.1 Creation of the Wrapper Interface Port;59
11.1.1;4.1.1 Creation of the WSP;59
11.1.2;4.1.2 Understanding the WPP;67
11.2;4.2 CTL Template for the Wrapper Interface Port;68
11.2.1;4.2.1 Structure of the CTL Internal block;70
11.3;4.3 Wrapper Interface Port Creation for the EX Core;79
11.3.1;4.3.1 Declaring WRCK for the EX wrapper in serial mode;83
11.3.2;4.3.2 Declaring WRSTN for the EX wrapper;84
11.3.3;4.3.3 Declaring SelectWIR for the EX Wrapper;85
11.3.4;4.3.4 Declaring ShiftWR for the EX Wrapper;85
11.3.5;4.3.5 Declaring CaptureWR for the EX wrapper;86
11.3.6;4.3.6 Declaring UpdateWR for the EX Wrapper;87
11.3.7;4.3.7 Declaring WSI for the EX Wrapper;88
11.3.8;4.3.8 Declaring WSO for the EX Wrapper;88
11.3.9;4.3.9 Declaring WPC for the EX Wrapper;89
11.3.10;4.3.10 Declaring WPI for the EX Wrapper;93
11.3.11;4.3.11 Declaring WPO for the EX Wrapper;95
11.4;4.4 Combined CTL Code for EX Wrapper Terminals;98
11.5;4.5 Plug-and-play of the 1500 Architecture;105
12;Chapter 5 Instruction Types;107
12.1;5.1 Overview of the IEEE 1500 Standard Instructions;107
12.1.1;5.1.1 Mandatory Instructions;109
12.1.2;5.1.2 Optional Instructions;113
12.1.3;5.1.3 User-Defined Instructions;118
12.2;5.2 EX Wrapped Core Instructions;119
12.3;5.3 CTL Template for 1500 Instructions;123
12.3.1;5.3.1 Describing Patterns in CTL;123
12.3.2;5.3.2 Accessing Information Outside the CTLMode Block Using the DomainReferences Keyword;128
12.3.3;5.3.3 Describing Test Modes Using the TestMode Keyword;129
12.3.4;5.3.4 Specifying Pattern Information for Test Modes Using the PatternInformation Keyword;130
12.3.5;5.3.5 Identifying IEEE 1500 Instructions Using the TestMode-ForWrapper Keyword;134
12.4;5.4 Combined 1500 Instructions CTL Code Template;134
12.5;5.5 Describing CTL Code for EX Wrapper Instructions;135
12.5.1;5.5.1 Describing WS_BYPASS in CTL for the EX Wrapper;136
12.5.2;5.5.2 Describing WP_BYPASS in CTL for the EX Core;141
12.5.3;5.5.3 Describing WS_EXTEST in CTL for the EX Core;143
12.5.4;5.5.4 Describing WP_INTEST in CTL for the EX core;145
12.5.5;5.5.5 Describing WS_INTEST in CTL for the EX Core;147
12.5.6;5.5.6 Describing WP_INTEST_MBIST in CTL for the EX core;149
12.5.7;5.5.7 Describing WP_EXTEST in CTL for the EX core;151
12.5.8;5.5.8 Describing WS_SAFE_SINGLE in CTL for the EX Core;153
12.5.9;5.5.9 Describing WP_EXTEST_SEQ in CTL for the EX Core;155
12.5.10;5.5.10 Describing WP_INTEST_SEQ in CTL for the EX core;157
13;Chapter 6 Design of the WBR;161
13.1;6.1 What is the WBR?;162
13.2;6.2 Provision of WBR cells;163
13.3;6.3 Creation of 1500 compliant WBR cells;164
13.3.1;6.3.1 WBR Cell operation;165
13.3.2;6.3.2 Dedicated WBR Cell implementation;170
13.3.3;6.3.3 Shared WBR Cell implementation;173
13.3.4;6.3.4 Harness Cells and Reduced Functionality Cells;175
13.4;6.4 Describing wrapper cells in 1500;176
13.4.1;6.4.1 Describing WBR cells;177
13.5;6.5 WBR Operation Events;181
13.5.1;6.5.1 WBR Operation Modes;182
13.5.2;6.5.2 Parallel configuration of the WBR;184
13.6;6.6 Creation of the WBR for the EX example;186
13.6.1;6.6.1 EX core test requirements;186
13.6.2;6.6.2 EX core WBR cell design;187
13.6.3;6.6.3 Shared WBR cell design;190
13.6.4;6.6.4 Special WBR cell design;192
13.6.5;6.6.5 WBR design;197
13.7;6.7 Describing the WBR in CTL;200
13.7.1;6.7.1 Describing WBR cells in CTL at a Wrapper Level;201
13.7.2;6.7.2 Describing WBR Cells in CTL at a Core Level;202
13.7.3;6.7.3 Describing Scan Chains in CTL;203
13.8;6.8 Describing the WBR chain of the EX wrapper in CTL;204
13.8.1;6.8.1 EX wrapper serial mode WBR chain;204
13.8.2;6.8.2 EX wrapper parallel mode WBR chains;205
13.9;6.9 Describing WBR Cells of the EX Wrapper in CTL;206
14;Chapter 7 Design of the WBY;211
14.1;7.1 Introduction;211
14.2;7.2 WBY Construction;211
14.3;7.3 WBY Utilization;214
14.4;7.4 WBY for the EX Core;215
14.5;7.5 Describing the WBY in CTL for the EX Core;215
15;Chapter 8 Design of the WIR;217
15.1;8.1 WIR architecture;217
15.1.1;8.1.1 WIR Operation;218
15.2;8.2 Understanding the WIR Rules;220
15.2.1;8.2.1 WIR Configuration and DR selection;220
15.2.2;8.2.2 Wrapper Disabled and Enabled States;221
15.2.3;8.2.3 WIR Design;221
15.3;8.3 Creation of the WIR for the EX example;226
15.3.1;8.3.1 Design of WIR building blocks;227
15.3.2;8.3.2 EX core WIR design;228
15.3.3;8.3.3 Design of WIR circuitry for 1500 register control;233
15.3.4;8.3.4 Design of WIR circuitry for register configuration;241
15.3.5;8.3.5 WIR circuitry for clock selection;245
15.4;8.4 Describing the WIR in CTL for the EX Core;246
16;Chapter 9 Hierarchical Cores;247
16.1;9.1 Dealing with Hierarchical Cores;247
16.2;9.2 WIR in a Hierarchical Core;248
16.3;9.3 WBY in a Hierarchical Core;248
16.4;9.4 WBR in a Hierarchical Core;250
17;Chapter 10 Finalizing the Wrapper Solution for the EX Core;251
17.1;10.1 Expressing Compliance to the 1500 Standard;251
17.1.1;10.1.1 Expressing 1500 compliance for the EX wrapper;252
17.2;10.2 The Wrapped Core;252
17.2.1;10.2.1 Wrapping the EX Core;252
17.3;10.3 Defining the wrapper reset operation in CTL;253
17.4;10.4 Pattern examples;255
17.4.1;10.4.1 WS_INTEST pattern example;255
17.4.2;10.4.2 WP_INTEST pattern example;257
17.5;10.5 Combined CTL Code for the EX Wrapper;259
18;Chapter 11 SOC Integration of 1500 Compliant Cores;279
18.1;11.1 SOC integration;279
18.1.1;11.1.1 1500 compliant wrapped core types.;279
18.1.2;11.1.2 Core connection types;281
18.1.3;11.1.3 Connecting 1500 compliant cores;283
18.1.4;11.1.4 Interfacing to SOC pins;287
18.2;11.2 TAP controller interface;291
18.2.1;11.2.1 Interfacing TAP FSM to WSC;292
18.2.2;11.2.2 Mapping TAP states to WIR events;294
18.2.3;11.2.3 Mapping TAP states to WBR cell events;296
18.3;11.3 Scheduling considerations;298
19;Conclusion;303
20;Index;305