Micheloni / Campardo / Olivo Memories in Wireless Systems

1. Auflage 2008
ISBN: 978-3-540-79078-5
Verlag: Springer-Verlag
Format: PDF
Kopierschutz: Adobe DRM (»Systemvoraussetzungen)

E-Book, Englisch, 310 Seiten

For the technological progress in communication technology it is necessary that the advanced studies in circuit and software design are accompanied with recent results of the technological research and physics in order to exceed its limitations. This book is a guide which treats many components used in mobile communications, and in particular focuses on non-volatile memories. It emerges following the conducting line of the non-volatile memory in the wireless system: On the one hand it develops the foundations of the interdisciplinary issues needed for design analysis and testing of the system. On the other hand it deals with many of the problems appearing when the systems are realized in industrial production. These cover the difficulties from the mobile system to the different types of non-volatile memories. The book explores memory cards, multichip technologies, and algorithms of the software management as well as error handling. It also presents techniques of assurance for the single components and a guide through the Datasheet lectures.

Autoren/Hrsg.

Micheloni, Rino

Campardo, Giovanni

Olivo, Piero

Inhaltsverzeichnis

1;Contents;7
2;About the Editors;9
3;Introduction;13
4;Hardware Platforms for Third-Generation Mobile Terminals;16
4.1;1.1 Introduction;16
4.2;1.2 Computation Units;18
4.3;1.3 The Memory System;23
4.4;1.4 The Display;29
4.5;1.5 The Transceiver;31
4.6;1.6 The Bus;36
4.7;1.7 Conclusions;41
4.8;References;42
5;Nonvolatile Memories: NOR vs. NAND Architectures;44
5.1;2.1 Introduction;44
5.2;2.2 The Read Operation in Flash Memories;45
5.3;2.3 Program Operation in Flash Memories;52
5.4;2.4 Erase Operation in Flash Memories;60
5.5;References;68
6;Nonvolatile Memories: Novel Concepts and Emerging Technologies;70
6.1;3.1 Introduction;70
6.2;3.2 Flash Technologies: Challenges and Perspectives;71
6.3;3.3 Emerging Nonvolatile Memories: Concepts, Materials and Architectures;76
6.4;References;80
7;Memory Cards;82
7.1;4.1 Introduction;82
7.2;4.2 Flash Card Description;85
7.3;4.3 The Standards on the Market;101
7.4;4.4 Multimedia Applications;106
7.5;References;108
8;Multichip;110
8.1;5.1 Introduction;110
8.2;5.2 Triple Stacked Multichip: from Feasibility Study to Samples;115
8.3;5.3 From Samples to Production;125
8.4;5.4 Evaluation of the Electrical Effects of the Package;129
8.5;5.5 Signal Integrity;132
8.6;5.6 How to Design a Substrate;134
8.7;5.7 How to Perform a Signal Integrity Analysis;135
8.8;5.8 Digital Signal Spectrum;136
8.9;5.9 Multichip Testing: Observability, Controllability, Reliability;138
8.10;5.10 Vertical Integration;142
8.11;5.11 Advanced Technological Solutions;145
8.12;References;147
9;Software Management of Flash Memories;150
9.1;6.1 Introduction;150
9.2;6.2 Software for Data Management on Flash Memories;151
9.3;6.3 Software Methodologies for Flash Memory Management;156
9.4;6.4 Code Storage;159
9.5;6.5 Common Problems in Flash Memory Software Management;160
9.6;6.6 SW Architectures;167
9.7;6.7 Disk Emulator;171
9.8;References;173
10;Error Correction Codes;174
10.1;7.1 Introduction;174
10.2;7.2 Error Sources in Flash Memories;175
10.3;7.3 Basic Concepts;176
10.4;7.4 ECC Effect on Error Probability;180
10.5;7.5 Hamming Code;183
10.6;7.6 Applications: NOR Flash Memory;186
10.7;7.7 Applications: MLC NOR Flash Memory;191
10.8;7.8 Algorithmic Hamming Code for Big Size Blocks;193
10.9;7.9 Conclusions;198
10.10;References;198
11;Board Level Reliability;200
11.1;8.1 Introduction;200
11.2;8.2 Bend Test;201
11.3;8.3 Drop Test;210
11.4;8.4 Thermal Cycling;231
11.5;References;233
12;Reliability in Wireless Systems;236
12.1;9.1 Introduction;236
12.2;9.2 Reliability Prediction Models (Phase 1);241
12.3;9.3 Reliability Improvement (Phase 2);248
12.4;9.4 Demonstration of Reliability Levels (Phase 3);250
12.5;9.5 Screening/Burn-In, Defectiveness and Fault Tolerance ( Phase 4);257
12.6;References;262
13;How to Read a Datasheet;264
13.1;10.1 Introduction;264
13.2;10.2 Contents of the First Page;264
13.3;10.3 Ball Out and Functional Block Diagram;266
13.4;10.4 Main Operations Allowed;268
13.5;10.5 Maximum Ratings and DC-AC Parameters;269
13.6;10.6 DC Parameters Benchmark Between Memories for the Multi- Chip;271
13.7;10.7 How to Read Timing Chart and AC Table;272
13.8;10.8 NOR Memory Read Timings;272
13.9;10.9 RAM Memory Read Timings;275
13.10;10.10 Read Timings for NAND Memory;275
13.11;10.11 NOR Memory Timings for Modify Operations;280
13.12;10.12 RAM Memory Timings for Modify Operations;283
13.13;10.13 NAND Memory Timings for Modify Operations;285
13.14;10.14 From Timing to Testing;287
13.15;References;288
14;Appendix A;300
14.1;A.1 Basic Elements;300
14.2;A.2 Read Operation;301
14.3;A.3 Program Operation;302
14.4;A.4 Erase Operation;302
14.5;A.5 Main Building Blocks of a Nonvolatile Memory;303
14.6;Bibliography;309
15;About the Authors;312
16;Index;320