Multi-run Memory Tests for Pattern Sensitive Faults

Softcover Nachdruck of the original 1. Auflage 2019
ISBN: 978-3-030-08198-0
Verlag: Springer International Publishing

Buch, Englisch, 135 Seiten, Previously published in hardcover, Format (B × H): 155 mm x 235 mm, Gewicht: 236 g

This book describes efficient techniques for production testing as well as for periodic maintenance testing (specifically in terms of multi-cell faults) in modern semiconductor memory. The author discusses background selection and address reordering algorithms in multi-run transparent march testing processes. Formal methods for multi-run test generation and many solutions to increase their efficiency are described in detail. All methods presented ideas are verified by both analytical investigations and numerical simulations.

- Provides the first book related exclusively to the problem of multi-cell fault detection by multi-run tests in memory testing process;

- Presents practical algorithms for design and implementation of efficient multi-run tests;

- Demonstrates methods verified by analytical and experimental investigations.

Zielgruppe

Research

Autoren/Hrsg.

Mrozek, Ireneusz

Fachgebiete

• Mathematik | Informatik EDV | Informatik Informatik Rechnerarchitektur
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise
• Mathematik | Informatik EDV | Informatik Technische Informatik

Inhaltsverzeichnis

Introduction to digital memory.- Basics of functional RAM testing.- Multi-cell faults.- Controlled random testing.- Multi-run tests based on background changing.- Multi-run tests based on address changing.- Multiple controlled random testing.- Pseudo exhaustive testing based on march tests.- Conclusion.

Über Autor(innen)

Ireneusz Mrozek received his M.Sc. and Ph.D. degrees in computer science in 1994 and 2004,respectively. Since 1994 he has been employed at the Faculty of Computer Science of Bialystok Technical University (Poland). His main research interests include the area of diagnostic testing of embedded memories. Particularly, he focuses on transparent tests for RAM as well as the application of these in the BIST or BISR schemes. He has also gained industrial experience working as a Senior Software Engineer at Motorola Solutions.