Nadler / Fry / Higinbotham Topics in Engineering Logic

International Series of Monographs on Electronics and Instrumentation
1. Auflage 2014
ISBN: 978-1-4831-8468-5
Verlag: Elsevier Science & Techn.
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 248 Seiten, Web PDF

Topics in Engineering Logic contains the lectures given at the Indian Statistical Institute in Calcutta, India, during the Spring of 1959. The lectures focus on a variety of topics related to engineering logic, including the use of the logical matrix as an auxiliary to the construction of various types of codes. Elementary logical circuits for synchronous systems are also considered, with emphasis on 'two-wire' systems based on static flip-flops and having various phase structures. Comprised of seven chapters, this volume begins with an introduction to the logical matrix, a form of representation of logical functions that permits rapid and clear solution of varied problems in logical design. The discussion then turns to elementary logical circuits for synchronous systems and their physical properties, with particular reference to contacts, diodes, and transistors as well as phase structures and diode-gated flip-flops for single-phase and two-phase applications. Subsequent chapters deal with a graphical approach based on the logical matrix as a method for reducing the canonic form to the two-level minimal form; codes and matrices; operational circuits; and the question of increasing reliability through structural redundance. The book concludes with several typical logical design problems, including a drum-indexing circuit and a series-parallel decimal multiplier. This monograph will be of interest to engineers.

Autoren/Hrsg.

Nadler, Morton

Fry, D. W.

Higinbotham, W. A.

Inhaltsverzeichnis

1;Front Cover;1
2;Topics in Engineering Logic;4
3;Copyright Page;5
4;Table of Contents;8
5;PREFACE;12
6;CHAPTER I. INTRODUCTION:
THE LOGICAL MATRIX;18
6.1;1. The logical variable;18
6.2;2. Logical functions;21
6.3;3. The logical matrix;22
6.4;4. Operations on logical matrices;27
6.5;5. Adjacency and k-cells, contact grids;33
6.6;6. The second canonic form;45
6.7;7. Symmetric functions;53
6.8;8. Other applications of the logical matrix;54
6.9;9. Multi-valued logic;56
6.10;10. The connexion matrix;57
6.11;Summary;58
7;CHAPTER II. PHYSICAL CONSIDERATIONS: ELEMENTARY LOGICAL CIRCUITS FOR SYNCHRONOUS SYSTEMS;59
7.1;1. Contacts, diodes and transistors;59
7.2;2. "Complete" logical elements;70
7.3;3. Phase structures;75
7.4;4. Diode-gated flip-flops for single-phase and two-phase application;82
7.5;5. Transistor gates for single-phase and two-phase logical
circuits;87
7.6;6. Transistor gates for direct-coupled logical circuits;88
7.7;7. Interconnexion of modes;94
7.8;Summary;95
8;CHAPTER III. THE MINIMAL FORM;97
8.1;1. Introductory remarks;97
8.2;2. The configuration code;99
8.3;3. Redundancies and operation counts;102
8.4;4. Preliminary definitions;104
8.5;5. Preparation of the matrix for minimization;106
8.6;6. Choice of &-cells: the first rule;106
8.7;7. Choice of k-cells: the second rule;111
8.8;8. Concrete gate synthesis;115
8.9;9. Switching functions for the case where the output variableenters into the function;116
8.10;Summary;118
9;CHAPTER IV. CODES AND MATRICES;119
9.1;1. Introduction;119
9.2;2. Hamming-distance codes;123
9.3;3. Decimal codes;142
9.4;4. Shift-register codes;145
9.5;5. Commaless codes;148
9.6;Summary;153
10;CHAPTER V. OPERATIONAL CIRCUITS;154
10.1;1. Circuit complexity;154
10.2;2. The operational circuit;156
10.3;3. Delay, output rate and critical functions;162
10.4;4. Upper bound on the complexity of maximally simplified critical functions;170
10.5;5. Critical functions and sequential circuits;174
10.6;6. The construction of auxiliary functions;176
10.7;Summary;185
11;CHAPTER VI. STRUCTURAL REDUNDANCE;186
11.1;1. Failure rates;186
11.2;2. Marginal checking;189
11.3;3. Microredundance;192
11.4;4. Maximum redundance;195
11.5;Appendix 1 : Statistics of microredundance (doubling);201
11.6;Appendix 2: Statistics of maximum redundance;203
11.7;Summary;204
12;CHAPTER VII. EXAMPLES;206
12.1;1. Drum-indexing circuit;206
12.2;2. Tape-to-drum buffer register;212
12.3;3. Bi-directional decimal counter;219
12.4;4. Series-parallel decimal multiplier;228
13;LIST OF REFERENCES;238
14;INDEX;244