Pavesi / Lockwood Silicon Photonics III

Systems and Applications
1. Auflage 2016
ISBN: 978-3-642-10503-6
Verlag: Springer
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, Band 122, 540 Seiten

Reihe: Topics in Applied Physics

This book is volume III of a series of books on silicon photonics. It reports on the development of fully integrated systems where many different photonics component are integrated together to build complex circuits. This is the demonstration of the fully potentiality of silicon photonics. It contains a number of chapters written by engineers and scientists of the main companies, research centers and universities active in the field. It can be of use for all those persons interested to know the potentialities and the recent applications of silicon photonics both in microelectronics, telecommunication and consumer electronics market.

David J. Lockwood earned BSc (1964), MSc (1966), and PhD (1969) degrees in physics at the University of Canterbury and was awarded a DSc in 2000. His doctoral research work was on inelastic light (Raman) scattering from insulators under Professor Alister G. McLellan. He spent 1970-71 as a post-doctoral fellow in physical chemistry with Professor Donald E. Irish at the University of Waterloo working on the vibrational spectroscopy of solvated cations. Dr. Lockwood then moved to Edinburgh University as a research fellow in the group of Professor William Cochran and spent six years there researching the dynamical properties of structural phase transitions and antiferromagnets. As a result of these studies he was awarded a DSc (1978) degree in physics by Edinburgh University. In 1978, Dr. Lockwood joined the Division of Physics of the National Research Council (NRC) of Canada, where he is now a Principal Research Officer in the Institute for Microstructural Sciences. At NRC, Dr. Lockwood continued his investigations of the electronic and magnetic excitations of antiferromagnets culminating in the classic book on light scattering in magnetic solids co-authored with Professor Michael G. Cottam. Since the mid-1980s he has researched the optical properties of semiconductor heterostructures, superlattices, and more recently, nanostructures. His seminal work on silicon nanostructures resulted in the definitive and widely cited observation of quantum-confined light emission in silicon and also of self-organized growth in superlattice structures. Dr. Lockwood has now published over 550 papers and 22 books on these topics and holds 7 patents. Dr. Lockwood has been extremely active in the promotion of science internationally through his service in recent years on more than 40 international and national committees including work within NATO, IUPAP, and the American Physical Society, where he was chair of the Forum on International Physics. He is an Editor of Solid State Communications and a member of the Editorial Boards of Physica E, Low Temperature Physics, The Open Condensed Matter Physics Journal, and Physics in Canada and is also Founding Editor for the Book Series on Nanostructure Science and Technology. Within the Electrochemical Society (ECS), he has co-organized or chaired a number of very successful international symposia on pits and pores, quantum confinement, and advanced luminescent materials and has served on the Board of Directors of ECS as well as chair of the Luminescence and Display Materials Division. He has served on the executive of the Canadian Association of Physicists as director of international affairs and also as treasurer, and of the Royal Society of Canada as treasurer. Dr. Lockwood is a Fellow of the Royal Society of Canada, the American Physical Society, and the Electrochemical Society, and is a member of the Materials Research Society, ASTM International, the Institute of Nanotechnology, and the Canadian Association of Physicists. In 2005 he was awarded the Brockhouse Medal of the Canadian Association of Physicists for outstanding achievement in condensed matter and materials physics and the Tory Medal of the Royal Society of Canada for outstanding research in any branch of astronomy, chemistry, mathematics, physics, or an allied science. Lorenzo Pavesi is Professor of Experimental Physics at the University of Trento (Italy). Born the 21st of November 1961, he received his PhD in Physics in 1990 at the Ecole Polytechnique Federale of Lausanne (Switzerland). In 1990 he became Assistant Professor, an Associate Professor in 1999 and Full Professor in 2002 at the University of Trento. He leads the nanoscience laboratory (25 people), teaches several classes at the Science Faculty of the University of Trento, and is dean of the PhD School in Physics. He founded the research activity in semiconductor optoelectronics at the University of Trento and started several laboratories of photonics, growth and advanced treatment of materials. He is in charge of the professional master in NEMS-MEMS, coorganized between University and FBK. He has directed more than 15 PhD students and more than 20 Master thesis students. His research activity concerned the optical properties of semiconductors. During the last years, he concentrated on Silicon based photonics where he looks for the convergence between photonics and electronics by using silicon nanostructures. He is interested in active photonics devices which can be integrated in silicon by using classical waveguides or novel waveguides such as those based on dynamical photonic crystals. His interests encompass also optical sensors or biosensors and solar cells. In silicon photonics, he is one of the worldwide recognized experts, he organized several international conferences, workshops and schools and is a frequently invited speaker. He manages several research projects, both national and international. He advises EC on photonics and is a frequently invited reviewer, monitor or referee for photonics projects by several grant agencies. He is an author or co-author of more than 250 papers, author of several reviews, editor of more than 10 books, author of 2 books and holds six patents. He is in the editorial board of Research Letters in Physics and he was in the editorial board of Journal of Nanoscience and Nanotechnologies, in the directive council of the LENS (Florence), in the Board of Delegates of E-MRS. He holds an H-number of 33 according to the web of science

Autoren/Hrsg.

Pavesi, Lorenzo

Lockwood, David J.

Inhaltsverzeichnis

1;Preface;6
2;Contents;9
3;Contributors;19
4;1 Silicon Optical Interposers for High-Density Optical Interconnects;24
4.1;Abstract;24
4.2;1.1 Introduction;24
4.2.1;1.1.1 Trends and Requirements of Computing Systems in Data Centers;24
4.2.2;1.1.2 Problems with Electrical Interconnects;25
4.2.3;1.1.3 Optical Interconnects with Silicon Photonics;26
4.2.4;1.1.4 Vision for on-Chip Servers;26
4.2.5;1.1.5 Photonics-Electronics Convergence System Technology (PECST) Project;27
4.3;1.2 Photonics--Electronics Convergence System for Inter-chip Interconnects;27
4.3.1;1.2.1 Optical Interconnects for Short Reach;27
4.3.2;1.2.2 Integration Between Photonics and Electronics;28
4.3.3;1.2.3 Light Source Integration;29
4.3.4;1.2.4 Photonics--Electronics Convergence System with Silicon Optical Interposers;31
4.4;1.3 Configuration and Characteristics of Optical Components for Silicon Optical Interposers;32
4.4.1;1.3.1 Silicon Optical Waveguides;32
4.4.2;1.3.2 Hybridly Integrated On-Chip Light Sources;33
4.4.2.1;1.3.2.1 Arrayed Laser Diodes;33
4.4.2.2;1.3.2.2 Spot-Size Converters;34
4.4.2.3;1.3.2.3 Flip-Chip Bonding of Arrayed LD Chip;35
4.4.3;1.3.3 Silicon Optical Modulators;37
4.4.4;1.3.4 Germanium Photodetectors;38
4.5;1.4 Silicon Optical Interposers for High Bandwidth Density;39
4.5.1;1.4.1 Design Consideration for Bandwidth Density and Optical Power Budget;39
4.5.2;1.4.2 Integrated Fabrication Process;40
4.5.3;1.4.3 Data Link Experiments;41
4.5.4;1.4.4 Significance of Bandwidth Density;43
4.6;1.5 Silicon Optical Interposers for Wide Temperature Range Operation;43
4.6.1;1.5.1 Hybridly Integrated Athermal Light Sources and Their Thermal Characteristics;44
4.6.2;1.5.2 Optical Modulators and Their Thermal Characteristics;46
4.6.3;1.5.3 Photodetectors and Their Thermal Characteristics;48
4.6.4;1.5.4 Data Link Experiments Over Wide Temperature Range;49
4.7;1.6 25-Gbps Data Links Using Silicon Optical Interposers and FPGA Transceivers;51
4.8;1.7 Advanced Fabrication Process and Optical Components for Wider Bandwidth in Future;53
4.8.1;1.7.1 Hybridly Integrated 1200-Channel Light Source;53
4.8.2;1.7.2 High-Speed Ring-Resonator-Based Optical Modulators;54
4.8.3;1.7.3 High-Speed Germanium Photodetectors with Low Contact Resistance;54
4.8.4;1.7.4 300-mm Wafer Processes with ArF Immersion Lithography for WDM;55
4.9;1.8 Perspectives on Inter-chip Interconnects;55
4.9.1;1.8.1 Vision for On-Board Datacenters;55
4.10;1.9 Optical I/O Cores;56
4.10.1;1.9.1 Further Efficient Interconnects for On-Board Datacenters;58
4.11;1.10 Conclusion;58
4.12;Acknowledgments;59
4.13;References;59
5;2 Silicon Quantum Photonics;63
5.1;Abstract;63
5.2;2.1 Introduction;63
5.2.1;2.1.1 Quantum Information;65
5.2.1.1;2.1.1.1 Entanglement;66
5.2.1.2;2.1.1.2 Path-Encoded Qubits;66
5.2.2;2.1.2 Optical Requirements for Quantum Applications;67
5.2.2.1;2.1.2.1 Photon Sources;68
5.2.2.2;2.1.2.2 Linear Optics;68
5.2.2.3;2.1.2.3 Single-Photon Detection;70
5.2.3;2.1.3 Scaling up Quantum Optics;70
5.2.4;2.1.4 Silicon Quantum Photonics;70
5.3;2.2 Linear Optics;71
5.3.1;2.2.1 Beam Splitter;72
5.3.1.1;2.2.1.1 Quantum Interference;72
5.3.1.2;2.2.1.2 Quantum Interference in Silicon Photonics;73
5.3.2;2.2.2 Phase Shifter;74
5.4;2.3 Photon Sources;75
5.4.1;2.3.1 Requirements for Photon Sources;76
5.4.2;2.3.2 A Brief Summary of SFWM Experiments in SOI;76
5.4.3;2.3.3 Theory of SFWM Sources;77
5.4.4;2.3.4 Silicon Waveguide Photon-Pair Sources;79
5.4.4.1;2.3.4.1 Phase Matching;79
5.4.4.2;2.3.4.2 Pair Generation Rate;80
5.4.4.3;2.3.4.3 Optimizing a Straight Waveguide Source for Brightness;81
5.4.4.4;2.3.4.4 Pair Generation Measurement;81
5.4.4.5;2.3.4.5 Analysis of Pair Generation Data;82
5.4.5;2.3.5 Ring Resonator;84
5.4.5.1;2.3.5.1 Optimization of the Ring Resonator for Pair Generation;87
5.4.5.2;2.3.5.2 Experimental Pair Generation in Ring Resonators;89
5.4.5.3;2.3.5.3 Joint Spectral Correlation and Source Purity;90
5.5;2.4 On-Chip Detectors;91
5.6;2.5 Integration;92
5.6.1;2.5.1 Multiple Sources;93
5.6.2;2.5.2 Sources and Filters;94
5.6.3;2.5.3 Multiple Sources and Interferometers;96
5.6.3.1;2.5.3.1 Integrated Path Entanglement Generation and Analysis;96
5.6.3.2;2.5.3.2 Entanglement Distribution Between Two SOI Chips;96
5.7;2.6 Outlook;97
5.7.1;2.6.1 Conclusion;97
5.8;References;98
6;3 Athermal Silicon Photonics;105
6.1;Abstract;105
6.2;3.1 Introduction;105
6.3;3.2 Background of Athermal Technology;106
6.3.1;3.2.1 Temperature-Dependent Wavelength Shift;106
6.3.2;3.2.2 Thermo-Optic Coefficient of Materials;107
6.3.3;3.2.3 Athermal Silica AWG;108
6.4;3.3 Athermal Silicon Photonics Using Polymer Cladding;110
6.5;3.4 Athermal Silicon Photonics Using Titania Cladding;115
6.6;3.5 Athermal Silicon MZI Without Negative TO Material;117
6.7;3.6 Summary;119
6.8;References;119
7;4 Design Flow Automation for Silicon Photonics: Challenges, Collaboration, and Standardization;121
7.1;Abstract;121
7.2;4.1 Silicon Photonics---History Repeats Itself;122
7.3;4.2 Photonic Integrated Circuit Design Methodologies and Flows;122
7.3.1;4.2.1 Front End Versus Building Blocks Methodology;123
7.3.2;4.2.2 Process Design Kit Driven Design;123
7.3.3;4.2.3 Overview of Flow---Comparison to Analog Design Flow;125
7.3.3.1;4.2.3.1 Schematic-Driven Layout;126
7.3.3.2;4.2.3.2 Design for Test and Manufacturability;127
7.3.3.3;4.2.3.3 Design Sensitivity;127
7.3.4;4.2.4 Schematic Capture;128
7.3.4.1;4.2.4.1 Interface to Simulation and Analysis;129
7.3.4.2;4.2.4.2 Matching Simulation to Layout;130
7.3.5;4.2.5 Photonic Circuit Modeling;130
7.3.5.1;4.2.5.1 Electronic Simulations Using SPICE;131
7.3.5.2;4.2.5.2 Electronic Versus Photonic Simulation;131
7.3.5.3;4.2.5.3 Photonic Circuit Simulation;132
7.3.5.4;4.2.5.4 Frequency Domain Analysis;134
7.3.5.5;4.2.5.5 Time Domain Analysis;135
7.3.6;4.2.6 Model Extraction for Compact Models;136
7.3.6.1;4.2.6.1 Methods and Challenges;137
7.3.6.2;4.2.6.2 Model Extraction from Physical Simulations;137
7.3.6.3;4.2.6.3 Compact Models in the Time Domain;137
7.3.6.4;4.2.6.4 Photonic Circuit Modeling Examples;138
7.3.7;4.2.7 Schematic-Driven Layout;138
7.3.7.1;4.2.7.1 Floorplanning;142
7.3.7.2;4.2.7.2 Routing;143
7.3.7.3;4.2.7.3 Specialty Design;143
7.3.8;4.2.8 Overview of Physical Verification for Silicon Photonics;144
7.3.8.1;4.2.8.1 Design Rule Checking;146
7.3.8.1.1;False Errors Induced by Curvilinear Structures;148
7.3.8.1.2;Multidimensional Rule Check on Tapered Structures;149
7.3.8.1.3;Density and Fill Insertion;151
7.3.8.2;4.2.8.2 Layout Versus Schematic;152
7.3.8.2.1;Challenges of Silicon Photonics for LVS;152
7.3.8.2.2;Adjustments to the LVS Flow;154
7.3.8.3;4.2.8.3 Parasitic Extraction;156
7.3.8.4;4.2.8.4 Design for Manufacturability;157
7.3.8.4.1;Lithographic Checking;158
7.3.8.4.2;PDKs for Silicon Photonics;160
7.4;4.3 Manufacturing and Lithography: Accuracy Problems and Process Variation;161
7.4.1;4.3.1 Silicon Photonics Fabrication Processes;161
7.4.2;4.3.2 Lithography;162
7.4.2.1;4.3.2.1 E-Beam Lithography;162
7.4.2.2;4.3.2.2 Deep UV Lithography;163
7.5;4.4 The ``CoDesign'' Problems;164
7.5.1;4.4.1 Co-layout;165
7.5.2;4.4.2 Co-simulation;165
7.5.3;4.4.3 Cointegration;166
7.5.4;4.4.4 Packaging;167
7.6;4.5 Standards Organizations Helping Evolve a Disintegrated Design, Manufacturing, Packaging, and Test Ecosystem;167
7.6.1;4.5.1 Photonics Fitting into EDA;167
7.6.2;4.5.2 Adding/Modifying for Photonics;168
7.6.3;4.5.3 Process Design Kits (PDKs);168
7.6.3.1;4.5.3.1 Electronic PDKs;169
7.6.3.2;4.5.3.2 Silicon Photonic PDKs;169
7.6.3.3;4.5.3.3 Current Scope with Strengths and Weaknesses;170
7.6.3.4;4.5.3.4 Outlook;171
7.6.3.5;4.5.3.5 Optoelectronics;171
7.6.4;4.5.4 Formats;172
7.6.5;4.5.5 Standards Development Organizations;172
7.6.5.1;4.5.5.1 Silicon Integration Initiative (Si2);172
7.6.5.2;4.5.5.2 PDAFlow Foundation;174
7.7;4.6 The Need for an Optoelectronic Unified Design Flow;174
7.8;4.7 Summary;176
7.9;References;176
8;5 Hardware--Software Integrated Silicon Photonics for Computing Systems;179
8.1;Abstract;179
8.2;5.1 Silicon Photonic Systems: A Subsystem Rationale;179
8.3;5.2 Chip-Scale Silicon Photonic Subsystems;180
8.3.1;5.2.1 Silicon Photonic Manufacturing Platforms;181
8.3.2;5.2.2 Photonic Packaging;181
8.3.3;5.2.3 End-to-End Connection in a Silicon Photonic Link;182
8.3.4;5.2.4 Systems Enabled by Programmable Logic Devices;184
8.3.5;5.2.5 System Considerations;185
8.4;5.3 Device Control for Thermal Stabilization;185
8.5;5.4 High-Speed Silicon Photonic Subsystems;186
8.5.1;5.4.1 Traveling-Wave Mach--Zehnder Modulator and Microring Modulators;187
8.5.2;5.4.2 Mach--Zehnder Interferometer and Microring Switches;189
8.5.3;5.4.3 Microring Performance Dependencies;190
8.6;5.5 Data Synchronization for Link-Based Delivery and Management;191
8.6.1;5.5.1 Burst Mode Data for Link Connections;191
8.6.2;5.5.2 Synchronization;192
8.6.3;5.5.3 Exploring Software Protocols for Circuit-Based Connection Management of Characterized Links;195
8.7;5.6 Hardware--Software Implementation for System Integration;197
8.7.1;5.6.1 Abstracting a Chip-Scale Silicon Photonic System;198
8.7.2;5.6.2 Software Control and Management;200
8.7.3;5.6.3 Example of Software Request-Grant-Based Control of Switched Silicon Photonic Circuits;203
8.7.4;5.6.4 Control-Centric Integration: Power-Optimized Silicon Photonic Spatial Switching;204
8.7.5;5.6.5 Network-Centric Integration: Programmable Wavelength Routing;206
8.8;5.7 Conclusion;208
8.9;Acknowledgments;208
8.10;References;208
9;6 Path to Silicon Photonics Commercialization: The Foundry Model Discussion;212
9.1;Abstract;212
9.2;6.1 Introduction;212
9.3;6.2 Silicon Photonics Technology Status;213
9.3.1;6.2.1 Fabless Semiconductor Model;213
9.3.2;6.2.2 Monolithic Integration Through CMOS Photonics;214
9.3.3;6.2.3 Technology Platform for Hybrid Integration;216
9.4;6.3 Role of Research and Development Foundries;220
9.4.1;6.3.1 Standardized Shuttle Runs;220
9.4.2;6.3.2 Customized Process Platform;223
9.4.3;6.3.3 Small Volume Production;223
9.5;6.4 Route to Commercialization;225
9.5.1;6.4.1 Manufacturing in CMOS Foundry;226
9.5.2;6.4.2 Process Qualification and Reliability;230
9.5.3;6.4.3 Outlook and Trends;231
9.6;6.5 Conclusion;233
9.7;Acknowledgment;234
9.8;References;234
10;7 Packaging of Silicon Photonic Devices;237
10.1;Abstract;237
10.2;7.1 Introduction;237
10.3;7.2 Optical Packaging;240
10.3.1;7.2.1 Fiber-Coupling;241
10.3.2;7.2.2 Grating-Coupling;242
10.3.3;7.2.3 Edge-Coupling;245
10.3.4;7.2.4 Laser Integration;246
10.3.5;7.2.5 Micro-Optic Hybrid Integration;247
10.3.6;7.2.6 VCSEL Hybrid Integration;248
10.4;7.3 Electrical Packaging;248
10.4.1;7.3.1 Packaging to PCB;249
10.4.1.1;7.3.1.1 3-D Electronic Packaging;249
10.4.1.2;7.3.1.2 2.5-D Electronic Packaging;252
10.5;7.4 Standardization;252
10.6;7.5 Conclusions;253
10.7;References;253
11;8 Silicon Photonics Packaging Automation: Problems, Challenges, and Considerations;257
11.1;Abstract;257
11.2;8.1 Introduction;257
11.3;8.2 Automated Fiber Array Pigtailing on Gratings;259
11.4;8.3 Optical Fiber Interface and Laser Integration on PICs: A Survey of Innovative Concepts and Automation Considerations;268
11.4.1;8.3.1 Optical Interface with External Fibers;269
11.4.1.1;8.3.1.1 Approach One;269
11.4.2;8.3.2 Approach Two;270
11.4.2.1;8.3.2.1 Approach Three;272
11.4.2.2;8.3.2.2 Approach Four;273
11.4.3;8.3.3 Laser Integration on PICs;276
11.5;8.4 Conclusions;278
11.6;References;278
12;9 CMOS Cost--Volume Paradigm and Silicon Photonics Production;280
12.1;Abstract;280
12.2;9.1 Introduction;280
12.3;9.2 Low Volume Production;282
12.3.1;9.2.1 Multi-project Wafers or MPWs for Affordable Prototyping;282
12.3.2;9.2.2 Commercial R&D Project;283
12.3.3;9.2.3 Corner Lot;284
12.3.4;9.2.4 Low Volume Production Lot;285
12.4;9.3 Markets and Volumes;285
12.4.1;9.3.1 Datacom;285
12.4.2;9.3.2 Telecom;287
12.4.3;9.3.3 Sensors;287
12.4.4;9.3.4 Volume Evolution;288
12.5;9.4 From Prototype to Volume Production: Technical Stages and Challenges;289
12.5.1;9.4.1 PDK and Design Flow;289
12.5.2;9.4.2 New Tape-Out (NTO);289
12.5.2.1;9.4.2.1 Floor Planning;290
12.5.2.2;9.4.2.2 Test Sites: Process Control and Functional Test;290
12.5.2.3;9.4.2.3 IP Blocks;290
12.5.2.4;9.4.2.4 Manufacturing Rule Check;291
12.5.2.5;9.4.2.5 Tiling and Fracturing;291
12.5.2.6;9.4.2.6 OPC, LFD, Biasing;291
12.5.2.7;9.4.2.7 Mask-Shop Communication;292
12.5.3;9.4.3 Flow Setup and Follow-up;292
12.5.4;9.4.4 Qualification and Yield Analysis;293
12.5.5;9.4.5 Dicing;293
12.5.6;9.4.6 Packaging and Reliability;294
12.6;9.5 Summary;294
12.7;References;294
13;10 Silicon Photonics Research and Manufacturing Using a 300-mm Wafer Platform;296
13.1;Abstract;296
13.2;10.1 Introduction;296
13.3;10.2 Industrialization Strategy and Electronics: Photonics Integration;298
13.3.1;10.2.1 Silicon Photonics Qualification Methodology;298
13.3.2;10.2.2 Electronics and Photonics Integration;299
13.3.3;10.2.3 Industrial Testing Strategy for Wafer Sorting;302
13.4;10.3 Photonics Process Integration and Process Control on 300 mm Wafers;304
13.4.1;10.3.1 Optical Component Patterning;305
13.4.2;10.3.2 Active Optical Component Definition;306
13.4.3;10.3.3 Middle of Line (MEOL) and Back End of Line (BEOL);306
13.4.4;10.3.4 Device Performance;306
13.4.5;10.3.5 Toward Optical Test Chip Development for Process and Performance Monitoring;307
13.4.5.1;10.3.5.1 Static Qualification Test Chips: Process Monitoring and 3-D FEBE Optical Compatibility;307
13.4.5.1.1;Process Monitoring;308
13.4.5.1.2;3-D FEBE Optical Compatibility;309
13.4.5.2;10.3.5.2 Dynamic Qualification Test Chips Without EIC: The Modulator Example;311
13.5;10.4 Design Kit and Spice Model Approach;313
13.5.1;10.4.1 Photonics Spice Model Development;314
13.5.1.1;10.4.1.1 Development Flow;314
13.5.1.2;10.4.1.2 Example: Phase Modulator and Photodiode;315
13.5.2;10.4.2 Spice Model Extraction Flow;317
13.5.3;10.4.3 Spice Models Hardware Correlation;317
13.5.3.1;10.4.3.1 The High-Speed Phase Modulator;317
13.5.3.2;10.4.3.2 The High-Speed Photo Detector;318
13.5.4;10.4.4 Spice Model Platform Capabilities;319
13.6;10.5 Process Exploration for Design and Performance Improvement;320
13.6.1;10.5.1 Improving Surface Coupling Efficiency;321
13.6.1.1;10.5.1.1 Substrate and Back Reflector Optimization;322
13.6.1.2;10.5.1.2 Substrate and Device Fabrication;323
13.6.1.3;10.5.1.3 Optical Characterization and Device Performance;323
13.6.2;10.5.2 Advanced Silicon Patterning;325
13.6.2.1;10.5.2.1 Limitation of Single Etched Waveguides;325
13.6.3;10.5.3 Application to Ring Modulator Devices;327
13.6.3.1;10.5.3.1 PN Versus PIN Architecture;328
13.6.3.2;10.5.3.2 Challenges in Ring Modulator Industrialization;328
13.6.3.3;10.5.3.3 Applications of Ring Modulators;330
13.7;References;331
14;11 Silicon Photonics-Based Signal Processing for Microwave Photonic Frontends;335
14.1;Abstract;335
14.2;11.1 Introduction;335
14.3;11.2 Silicon-Based Signal Processors;336
14.3.1;11.2.1 FIR Signal Processors;337
14.3.1.1;11.2.1.1 Silicon-on-Insulator (SOI) FIR Signal Processor Based on Cascaded MZIs;337
14.3.1.2;11.2.1.2 Si3N4 FIR Signal Processor [22, 23];340
14.3.2;11.2.2 IIR Signal Processors;344
14.3.2.1;11.2.2.1 Si3N4 Microring IIR Filter [29];344
14.3.3;11.2.3 FIR/IIR Hybrid Signal Processors;345
14.4;11.3 Silicon Photonics-Based Photonic Frontends;349
14.4.1;11.3.1 Parallel Down-Conversion Frontends [29];349
14.4.2;11.3.2 OEO Frontends;351
14.5;11.4 Photonic-Assisted SDR Transceiver;356
14.6;11.5 Conclusions;362
14.7;Acknowledgements;363
14.8;References;363
15;12 Advanced Silicon Photonics Transceivers;366
15.1;Abstract;366
15.2;12.1 Introduction;366
15.3;12.2 Silicon Photonics for Optical Interconnect;367
15.4;12.3 Silicon Photonics Technology Advancements;368
15.4.1;12.3.1 Silicon Photonics Wafer Processing Flow;368
15.4.2;12.3.2 Silicon Photonics Devices;371
15.4.3;12.3.3 2.5 D Integration for Combining Electronic and Photonic Circuits;374
15.4.4;12.3.4 Wafer-Scale Optical Probing of Silicon Photonics;375
15.5;12.4 Advanced Optical Transceiver Design in Silicon Photonics Technology;378
15.5.1;12.4.1 Design Infrastructure: Design Kit;378
15.5.2;12.4.2 Transmitter Design;379
15.5.3;12.4.3 Receiver Design;381
15.5.4;12.4.4 Transceiver Architecture;382
15.6;12.5 Light Source for Silicon Photonics;384
15.7;12.6 Packaging;388
15.8;12.7 Conclusions;389
15.9;Acknowledgements;389
15.10;References;390
16;13 Optical Transceivers Using Heterogeneous Integration on Silicon;392
16.1;Abstract;392
16.2;13.1 Introduction;392
16.3;13.2 Heterogeneous Integration;393
16.3.1;13.2.1 Components;396
16.3.2;13.2.2 Lasers;396
16.3.3;13.2.3 Semiconductor Optical Amplifiers;397
16.3.4;13.2.4 Modulators;398
16.3.5;13.2.5 Photodiodes;399
16.3.6;13.2.6 Circuits;400
16.4;13.3 Packaging;407
16.5;13.4 Conclusion;411
16.6;References;411
17;14 Merits and Potential Impact of Silicon Photonics;413
17.1;Abstract;413
17.2;14.1 Technical Merits of Silicon Photonic Devices;414
17.2.1;14.1.1 High-Index-Contrast Silicon Waveguides;414
17.2.2;14.1.2 High Integration Level of Silicon Photonics;416
17.2.3;14.1.3 High Yield and Low Cost by Mature CMOS Fabrication;417
17.3;14.2 Applications;419
17.3.1;14.2.1 Telecommunication Applications;419
17.3.2;14.2.2 DataComm Applications;422
17.3.3;14.2.3 Chip-Scale Interconnects;424
17.4;14.3 Silicon Photonic Integrated Circuits;426
17.4.1;14.3.1 WDM Transmitters;426
17.4.2;14.3.2 WDM Receivers;428
17.4.3;14.3.3 Coherent Optical Transmitters;429
17.4.4;14.3.4 Coherent Optical Receivers;430
17.5;14.4 Conclusion;432
17.6;References;433
18;15 Silicon Photonics for Telecom and Datacom Applications;437
18.1;Abstract;437
18.2;15.1 Introduction;438
18.3;15.2 Optical Switching Devices for Access and Mobile Networks;438
18.3.1;15.2.1 Silicon Integrated Mini-ROADM;441
18.3.2;15.2.2 Silicon Integrated Devices for Multidirectional ROADMs;445
18.4;15.3 High Scale Photonic Integrated Device for Optical Switching in Metro Transport Nodes and Data Centers;448
18.4.1;15.3.1 Silicon Photonics Integrated TPA: IRIS Project;452
18.4.1.1;15.3.1.1 TPA Block Diagram;455
18.4.1.2;15.3.1.2 Optical Switching in Data Centers;457
18.5;15.4 Perspectives and Research Directions;459
18.6;References;460
19;16 Is Silicon Photonics a Competitive Technology to Enable Better and Highly Performing Networks?;463
19.1;Abstract;463
19.2;16.1 Introduction;464
19.3;16.2 Fundamental Characteristics of Rib-Waveguide Phase Shifter;465
19.3.1;16.2.1 Rib-Waveguide Phase Shifter in MZ Interferometer;465
19.3.2;16.2.2 Optical Loss Characteristics;467
19.3.3;16.2.3 Series Resistance Reduction for Shorter RC Delay;471
19.3.4;16.2.4 EO Response;473
19.4;16.3 Free-Carrier Plasma Dispersion for High-Speed Silicon Optical Modulator;474
19.4.1;16.3.1 Energy Transfer in Drude Theory;474
19.4.2;16.3.2 TEC-Free DC Optical Characteristics;476
19.4.3;16.3.3 Frequency Chirping;476
19.5;16.4 Silicon Optical Modulators in High-Capacity Optical Networks;478
19.5.1;16.4.1 On-off Keying Characteristics;478
19.5.2;16.4.2 Phase-Shift Keying Characteristics;480
19.5.2.1;16.4.2.1 Bpsk;480
19.5.2.2;16.4.2.2 Qpsk;481
19.5.2.3;16.4.2.3 Dp-Qpsk;482
19.6;16.5 Conclusion;485
19.7;References;485
20;17 Silicon Photonics Technologies: Gaps Analysis for Datacenter Interconnects;489
20.1;Abstract;489
20.2;17.1 Introduction;489
20.2.1;17.1.1 The New Internet;489
20.2.2;17.1.2 Datacenter Network Architecture;491
20.3;17.2 Performance Metrics for Intra-datacenter Interconnect;492
20.3.1;17.2.1 Cost;492
20.3.2;17.2.2 Power, Density, Size;494
20.3.3;17.2.3 Cable Efficiency;496
20.3.4;17.2.4 Latency;497
20.3.5;17.2.5 Serviceability: Pluggable Versus Embedded Transceivers;498
20.3.6;17.2.6 Performance;501
20.4;17.3 Conclusion;502
20.5;References;503
21;18 VLSI Photonics for High-Performance Data Centers;505
21.1;Abstract;505
21.2;18.1 Photonic-Interconnected Data Center Architectures;506
21.3;18.2 Si Microring-Based Transceivers;512
21.4;18.3 Hybrid III--V-on-Si Transceivers;516
21.5;References;527
22;Index;533