E-Book, Englisch, 491 Seiten
Reihe: Embedded Multi-Core Systems
Qadri / Sangwine Multicore Technology
1. Auflage 2013
ISBN: 978-1-4398-8064-7
Verlag: Taylor & Francis
Format: PDF
Kopierschutz: Adobe DRM (»Systemvoraussetzungen)
Architecture, Reconfiguration, and Modeling
E-Book, Englisch, 491 Seiten
Reihe: Embedded Multi-Core Systems
ISBN: 978-1-4398-8064-7
Verlag: Taylor & Francis
Format: PDF
Kopierschutz: Adobe DRM (»Systemvoraussetzungen)
The saturation of design complexity and clock frequencies for single-core processors has resulted in the emergence of multicore architectures as an alternative design paradigm. Nowadays, multicore/multithreaded computing systems are not only a de-facto standard for high-end applications, they are also gaining popularity in the field of embedded computing.
The start of the multicore era has altered the concepts relating to almost all of the areas of computer architecture design, including core design, memory management, thread scheduling, application support, inter-processor communication, debugging, and power management. This book gives readers a holistic overview of the field and guides them to further avenues of research by covering the state of the art in this area. It includes contributions from industry as well as academia.
Autoren/Hrsg.
Fachgebiete
Weitere Infos & Material
Architecture and Design Flow: MORA: High-Level FPGA Programming Using a Many-core Framework. Implementing Time-Constrained Applications on a Predictable MPSoc. SESAM Prototyping Solution. Parallelism and Optimization: Verified Multicore Parallelism using Atomic Verifiable Operations. Accelerating Critical Section Execution with Multi-Core Architectures. Memory Systems: TMbox: Hybrid Transactional Memory System. EM2: A Scalable Shared Memory Architecture for Largescale Multicores. CAFÉ: Cache-Aware Fair and Efficient Scheduling for CMPs. Debugging: Software Debugging Infrastructure for Multi-Core Systems-on-Chip. Networks-on-Chip: On Chip Interconnects for Multi-Core Architectures. Routing in Multi-Core NoCs. Efficient Topologies for 3-D Networks-on-Chip. Network-on-Chip Performance Evaluation using an Analytical Method. Bibliography. Index.
