Roermund / Steyaert / Casier Analog Circuit Design

Smart Data Converters, Filters on Chip, Multimode Transmitters
1. Auflage 2009
ISBN: 978-90-481-3083-2
Verlag: Springer Netherlands
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 342 Seiten

Analog Circuit Design contains the contribution of 18 tutorials of the 18th workshop on Advances in Analog Circuit Design. Each part discusses a specific to-date topic on new and valuable design ideas in the area of analog circuit design. Each part is presented by six experts in that field and state of the art information is shared and overviewed. This book is number 18 in this successful series of Analog Circuit Design, providing valuable information and excellent overviews of: Smart Data Converters: Chaired by Prof. Arthur van Roermund, Eindhoven University of Technology, Filters on Chip: Chaired by Herman Casier, AMI Semiconductor Fellow, Multimode Transmitters: Chaired by Prof. M. Steyaert, Catholic University Leuven, Analog Circuit Design is an essential reference source for analog circuit designers and researchers wishing to keep abreast with the latest development in the field. The tutorial coverage also makes it suitable for use in an advanced design.

Prof. Arthur van Roermund and Prof. Michiel Steyaert have been editing the best papers from the yearly Advances in Analog Circuit Design workshop into a book for the past 5 years. Dr. Herman Casier is new to the editing trio, he brings excellent input from industry.

Autoren/Hrsg.

Steyaert, Michiel

Casier, Herman

Roermund, Arthur H. M. Van

Inhaltsverzeichnis

1;Analog Circuit Design
;1
1.1;Preface
;4
1.2;Series on Integrated Circuits and Systems;4
1.3;Part I Smart Data Converters;8
1.3.1;1 LMS-Based Digital Assisting for Data Converters;9
1.3.1.1;1.1 Introduction;9
1.3.1.2;1.2 High-Resolution ADCs;10
1.3.1.3;1.3 Limits of ADC Resolution;13
1.3.1.4;1.4 Zero-Forcing LMS Algorithm;14
1.3.1.5;1.5 LMS-Based Calibration of the Pipelined ADC;15
1.3.1.5.1;1.5.1 Measurement Time and Dither Magnitude Constraints;16
1.3.1.5.2;1.5.2 Signal-Dependent Dithering Under Two Constraints;17
1.3.1.5.3;1.5.3 Linearity Improvement;19
1.3.1.5.4;1.5.4 Opamp Non-linearity Calibration;20
1.3.1.6;1.6 Noise Leakage Calibration in CT Cascaded Modulator;21
1.3.1.6.1;1.6.1 CT-to-DT Transform;22
1.3.1.6.2;1.6.2 Calibrated Cascaded Modulator;23
1.3.1.7;1.7 Conclusions;25
1.3.1.8;References;26
1.3.2;2 Pipelined ADC Digital Calibration Techniques and Tradeoffs;28
1.3.2.1;2.1 Introduction;28
1.3.2.2;2.2 Review of Error Sources in Pipelined ADCs;29
1.3.2.2.1;2.2.1 Gain Errors;29
1.3.2.2.2;2.2.2 DAC Errors;31
1.3.2.3;2.3 Digital Calibration Techniques;31
1.3.2.3.1;2.3.1 Digital Gain Error Calibration;32
1.3.2.3.2;2.3.2 DAC Gain Error Calibration;32
1.3.2.3.3;2.3.3 Foreground Calibration Techniques;33
1.3.2.3.4;2.3.4 Background Calibration;34
1.3.2.4;2.4 Rapid Background Calibration Techniques;35
1.3.2.4.1;2.4.1 Slow but Accurate Parallel ADC;35
1.3.2.4.2;2.4.2 Split-ADC Gain Error Calibration;36
1.3.2.4.3;2.4.3 Rapid DAC and Gain Error Correction;37
1.3.2.5;2.5 Using Digital Calibration to Build Low Power `Smart-ADCs';41
1.3.2.5.1;2.5.1 Open Loop, Non-linear Gain Error Calibration;41
1.3.2.5.2;2.5.2 Capacitive Charge Pump Based Pipelined ADC;43
1.3.2.6;2.6 Summary;46
1.3.2.7;References;46
1.3.3;3 High-Resolution and Wide-Bandwidth CMOS Pipeline AD Converters;48
1.3.3.1;3.1 Introduction;48
1.3.3.2;3.2 Digital Calibration of Non-Linearity;50
1.3.3.2.1;3.2.1 DAC Non-linearity;51
1.3.3.2.2;3.2.2 Stage Gain Non-linearity;52
1.3.3.3;3.3 Range-Scaling in the First Pipeline Stage;53
1.3.3.3.1;3.3.1 Power Consumption in a Noise-Limited ADC;53
1.3.3.3.2;3.3.2 Circuit Implementation;54
1.3.3.4;3.4 SHA-Less Architecture;55
1.3.3.5;3.5 A 1.2V 14b 100MS/s ADC in 90nm CMOS;56
1.3.3.5.1;3.5.1 ADC Architecture;57
1.3.3.5.2;3.5.2 Measured Results;58
1.3.3.6;3.6 Conclusions;63
1.3.3.7;References;63
1.3.4;4 A Signal Processing View on Time-Interleaved ADCS;65
1.3.4.1;4.1 Introduction;65
1.3.4.2;4.2 Time-Interleaved ADCs;66
1.3.4.3;4.3 Modeling Time-Interleaved ADCs;67
1.3.4.4;4.4 Digital Calibration of Linear Channel Mismatches;70
1.3.4.4.1;4.4.1 Digital Correction Methods;71
1.3.4.4.1.1;4.4.1.1 Time Offset Mismatches;72
1.3.4.4.1.2;4.4.1.2 Frequency Response Mismatches;75
1.3.4.4.2;4.4.2 Digital Identification Methods;77
1.3.4.4.2.1;4.4.2.1 Off-line Identification;78
1.3.4.4.2.2;4.4.2.2 On-line Identification;79
1.3.4.5;4.5 Conclusions;81
1.3.4.6;References;81
1.3.5;5 DAC Correction and Flexibility, Classification, New Methods and Designs;83
1.3.5.1;5.1 Introduction;83
1.3.5.2;5.2 Correction Methods for Current-Steering DACs;84
1.3.5.2.1;5.2.1 Classification;84
1.3.5.2.2;5.2.2 New Correction Methods Based on Parallel Sub-DACs;87
1.3.5.2.2.1;5.2.2.1 New Method 1: High Level Mapping;87
1.3.5.2.2.2;5.2.2.2 New Method 2: Suppression of Harmonic Distortion;88
1.3.5.2.2.3;5.2.2.3 New Method 3: Self-Calibration of Binary Currents;90
1.3.5.3;5.3 Analysis of DAC Self-Calibration Methods;91
1.3.5.3.1;5.3.1 Self-Measurement Block;91
1.3.5.3.2;5.3.2 Algorithm Block;92
1.3.5.3.3;5.3.3 Self-Correction Block;94
1.3.5.4;5.4 Parallel Current-Steering DACs for Flexibility and Smartness;95
1.3.5.5;5.5 Design Examples and Measurements;97
1.3.5.5.1;5.5.1 Unary Currents Self-Calibration in a 12-bit 250nm DAC;97
1.3.5.5.2;5.5.2 Both Unary and Binary Currents Self-Calibration in a 12-bit 180nm Quad-Core Flexible DAC;102
1.3.5.6;5.6 Conclusions;106
1.3.5.7;References;108
1.3.6;6 Smart CMOS Current-Steering D/A-Converters for Embedded Applications;110
1.3.6.1;6.1 Introduction;110
1.3.6.2;6.2 A Multimode -DAC;112
1.3.6.3;6.3 A 13-b 200MS/s Background-Calibrated DAC;116
1.3.6.3.1;6.3.1 Converter Architecture;117
1.3.6.3.2;6.3.2 Segment Boundary Calibration;118
1.3.6.3.3;6.3.3 Randomization of the Calibration Period;120
1.3.6.3.4;6.3.4 Low-Bandwidth High-Resolution Mode;121
1.3.6.4;6.4 A 13-b 50MHz Bandwidth DAC with Active Output Stage;123
1.3.6.4.1;6.4.1 Converter Architecture;124
1.3.6.4.2;6.4.2 Direct Segment Calibration;124
1.3.6.5;6.5 Conclusions;128
1.3.6.6;References;128
1.4;Part II Filters On-Chip;130
1.4.1;7 Synthesis of Low-Sensitivity Analog Filters;131
1.4.1.1;7.1 Introduction;131
1.4.1.2;7.2 Passive Filters;132
1.4.1.2.1;7.2.1 Doubly Resistively Terminated Lossless Networks;132
1.4.1.2.2;7.2.2 Reflection Function;133
1.4.1.2.3;7.2.3 Sensitivity;134
1.4.1.2.4;7.2.4 Passband Sensitivity;134
1.4.1.3;7.3 Errors in the Elements in Doubly Terminated Filters;138
1.4.1.3.1;7.3.1 Errors in the Terminating Resistors;140
1.4.1.3.2;7.3.2 Effects of Lossy Elements;141
1.4.1.4;7.4 LC Filters with Diminishing Ripple;142
1.4.1.5;7.5 Approximations with Small Group Delay;143
1.4.1.6;7.6 Design of Doubly Terminated LC Filters;146
1.4.1.7;7.7 Conclusions;147
1.4.1.8;References;147
1.4.2;8 High-Performance Continuous-Time Filters with On-Chip Tuning;148
1.4.2.1;8.1 Introduction;148
1.4.2.2;8.2 Linear Operational Transconductance Amplifiers (OTAs);149
1.4.2.2.1;8.2.1 Advanced Linearization Techniques;150
1.4.2.2.2;8.2.2 OTA Linearization Using Non-linear Elements;151
1.4.2.2.3;8.2.3 Design Example: A 30-MHz Elliptic Filter;154
1.4.2.3;8.3 Broadband Tuning for Interference Suppression in UWB Receivers;155
1.4.2.3.1;8.3.1 Analog LMS Control for Maximizing Attenuation;158
1.4.2.3.2;8.3.2 Interference Detection and Center Frequency Tuning;160
1.4.2.3.3;8.3.3 Experimental Results;161
1.4.2.4;8.4 Calibration of the Noise Transfer Function in a BP Modulator;162
1.4.2.5;8.5 Conclusion;165
1.4.2.6;References;166
1.4.3;9 Source-Follower-Based Continuous Time Analog Filters;168
1.4.3.1;9.1 Introduction;168
1.4.3.2;9.2 Source-Follower Circuit;170
1.4.3.3;9.3 A Source-Follower-Based Cascade CT Filter;172
1.4.3.3.1;9.3.1 Linearity Performance;174
1.4.3.3.2;9.3.2 Noise Performance;175
1.4.3.3.3;9.3.3 DC-Gain Loss;175
1.4.3.3.4;9.3.4 Minimum Supply Voltage;176
1.4.3.3.5;9.3.5 Silicon Prototype Experimental Results: A Fourth-Order Cascade SFB CT Filter for WLAN Receivers;176
1.4.3.4;9.4 A Source-Follower-Based Ladder CT Filter;180
1.4.3.4.1;9.4.1 Filter Circuital Topology;182
1.4.3.4.2;9.4.2 Minimum Supply Voltage;182
1.4.3.4.3;9.4.3 Silicon Prototype Experimental Results: A Sixth-Order Ladder SFB CT Filter for UWB Receivers;182
1.4.3.5;9.5 Conclusions;186
1.4.3.6;References;187
1.4.4;10 Reconfigurable Active-RC Filters with High Linearity and Low Noise for Home Networking Applications;189
1.4.4.1;10.1 Introduction;189
1.4.4.2;10.2 Architecture Selection;190
1.4.4.3;10.3 Architectural-Level Design Considerations;192
1.4.4.3.1;10.3.1 Optimized for Noise;192
1.4.4.3.2;10.3.2 Optimized for Speed;192
1.4.4.3.3;10.3.3 Optimized for Linearity;193
1.4.4.4;10.4 Circuit-Level Design Considerations;193
1.4.4.4.1;10.4.1 Reconfigurable Filter and Gain Stages;194
1.4.4.4.2;10.4.2 PGA Opamps with Adaptive Compensation;195
1.4.4.4.3;10.4.3 Tuning Loops;196
1.4.4.5;10.5 Experimental Results;197
1.4.4.6;10.6 Conclusions;201
1.4.4.7;References;201
1.4.5;11 On-Chip Instantaneously Companding Filters for Wireless Communications;203
1.4.5.1;11.1 Introduction;203
1.4.5.2;11.2 Companding Switched Capacitor Filter Implementation;205
1.4.5.3;11.3 Opamp's DC Offset Cancellation;211
1.4.5.4;11.4 WLAN Receiver Baseband Signal Chain;214
1.4.5.5;11.5 Simulation Results;215
1.4.5.6;11.6 Summary;217
1.4.5.7;References;218
1.4.6;12 BAW-IC CO-Integration Tunable Filters at GHz Frequencies;219
1.4.6.1;12.1 Introduction;219
1.4.6.2;12.2 BAW Technology;220
1.4.6.2.1;12.2.1 BAW Resonators;220
1.4.6.2.2;12.2.2 Electromechanical and Electrical Model of a BAW Resonator;221
1.4.6.3;12.3 BAW Resonator Filters;222
1.4.6.3.1;12.3.1 BAW Ladder Filters;223
1.4.6.3.2;12.3.2 BAW Lattice Filters;223
1.4.6.3.3;12.3.3 BAW Filters Synthesis Method;225
1.4.6.4;12.4 Tunable BAW Resonators;226
1.4.6.5;12.5 Design of an Electronically Tunable BAW Filter for Zero IF W-CDMA Receivers;228
1.4.6.5.1;12.5.1 BAW Tuning Cell Implementation;229
1.4.6.5.2;12.5.2 BAW Filter Implementation;231
1.4.6.5.3;12.5.3 BAW Filter Measurement Results;233
1.4.6.6;12.6 Tuning Circuitry for BAW Filters;234
1.4.6.6.1;12.6.1 Preliminary Discussion;234
1.4.6.6.2;12.6.2 Indirect Tuning Method I: PLL with a VCO as Master Cell;236
1.4.6.6.3;12.6.3 Indirect Tuning Method II: FLL with Envelope Detection;237
1.4.6.7;12.7 Design of a Digital Tuning Circuitry for a BAW Tunable Filter;238
1.4.6.7.1;12.7.1 Circuit Implementation;239
1.4.6.7.2;12.7.2 Measurement Results;240
1.4.6.8;12.8 Conclusions and Perspectives;242
1.4.6.9;References;243
1.5;Part III Multi-mode Transmitters;245
1.5.1;13 Multimode Transmitters: Easier with Strong Nonlinearity;247
1.5.1.1;13.1 Introduction;247
1.5.1.2;13.2 Architecture;248
1.5.1.3;13.3 Design Issues;249
1.5.1.4;13.4 Performance Measurements;253
1.5.1.5;13.5 Conclusions;256
1.5.1.6;References;257
1.5.2;14 RBS High Efficiency Power Amplifier Research – Challenges and Possibilities;258
1.5.2.1;14.1 Introduction;258
1.5.2.2;14.2 Power Amplifier Efficiency in an RBS Transmitter Context;259
1.5.2.3;14.3 Software Defined Radio (SDR) RBS;260
1.5.2.3.1;14.3.1 SDR RBS;260
1.5.2.4;14.4 Wide RF Bandwidth Power Amplifier Design;261
1.5.2.5;14.5 Efficiency Enhancement Techniques;263
1.5.2.5.1;14.5.1 Envelope Tracking Transmitter Architecture;265
1.5.2.5.2;14.5.2 Third Order Doherty;266
1.5.2.5.3;14.5.3 Pulsed Transmitter Architectures;267
1.5.2.5.3.1;14.5.3.1 Three Examples of Pulsed Transmitter Architectures;269
1.5.2.5.3.1.1;Baseband or Envelope PM;269
1.5.2.5.3.1.2;Cartesian PM;269
1.5.2.5.3.1.3;RF PM;270
1.5.2.5.3.2;14.5.3.2 Efficient Filtering of the Residual Quantization Distortion;271
1.5.2.6;14.6 Conclusions;271
1.5.2.7;References;272
1.5.3;15 Multi-Mode Transmitters in CMOS;273
1.5.3.1;15.1 Introduction;273
1.5.3.2;15.2 Direct Quadrature Voltage Modulator for Cellular Applications;274
1.5.3.2.1;15.2.1 Direct Quadrature Voltage Modulator;275
1.5.3.2.2;15.2.2 25% Duty-Cycle LO Generation;277
1.5.3.2.3;15.2.3 Measurement Results;278
1.5.3.3;15.3 Digital Polar Transmitter for Connectivity Applications;281
1.5.3.3.1;15.3.1 Direct Digital Polar Transmitter;284
1.5.3.3.2;15.3.2 Multi-phase Clocking;285
1.5.3.3.3;15.3.3 IC Implementation;286
1.5.3.3.4;15.3.4 Measurement Results;289
1.5.3.4;15.4 Conclusions;291
1.5.3.5;References;291
1.5.4;16 Challenges for Mobile Terminal CMOS Power Amplifiers;293
1.5.4.1;16.1 Introduction;293
1.5.4.2;16.2 Efficiency Improvement Techniques;294
1.5.4.3;16.3 Changing the RF Path;294
1.5.4.3.1;16.3.1 Discrete Class B;296
1.5.4.3.2;16.3.2 Power Combining;296
1.5.4.4;16.4 Changing the BB Path;298
1.5.4.4.1;16.4.1 Digital Polar;300
1.5.4.5;16.5 Conclusions;301
1.5.4.6;References;301
1.5.5;17 Multimode Transmitters with -Based All-Digital RF Signal Generation;303
1.5.5.1;17.1 Introduction;303
1.5.5.2;17.2 Modulation for All-Digital RF Signal Generation;305
1.5.5.2.1;17.2.1 What Can Modulation Bring in Integrated Transmitters?;305
1.5.5.2.2;17.2.2 IF DAC;306
1.5.5.2.3;17.2.3 1-bit RF DAC;306
1.5.5.2.4;17.2.4 Multi-bit RF DAC;307
1.5.5.3;17.3 Switched Power Amplification;308
1.5.5.3.1;17.3.1 Current and Voltage-Mode Switched Power Amplifier;308
1.5.5.3.2;17.3.2 Power Combining;309
1.5.5.4;17.4 Discussion on Digital and Mixed-Signal Blocks Implementation;311
1.5.5.4.1;17.4.1 Oversampling Up to RF Frequencies;311
1.5.5.4.2;17.4.2 Sampling Clock Synchronization on RF LO;311
1.5.5.4.3;17.4.3 Implementing the Modulator;312
1.5.5.4.3.1;17.4.3.1 Pipelined MASH Structures;312
1.5.5.4.3.2;17.4.3.2 High-Speed Modulator Implementation Using Redundant Representation;313
1.5.5.4.3.3;17.4.3.3 Going Further: Adaptive Placement of Complex Poles and Zeros of the NTF;314
1.5.5.4.4;17.4.4 Mixer and Digital-to-Analog Conversion;315
1.5.5.5;17.5 Dealing with Quantization Noise;316
1.5.5.5.1;17.5.1 BAW Filtering;316
1.5.5.5.2;17.5.2 RF Semi-Digital FIR Filtering;317
1.5.5.6;17.6 Conclusion;319
1.5.5.7;References;320
1.5.6;18 Switched Mode Transmitter Architectures;322
1.5.6.1;18.1 Introduction;322
1.5.6.2;18.2 Power Amplifiers;325
1.5.6.3;18.3 Envelope Modulation Techniques;327
1.5.6.4;18.4 Polar Switched Mode Architectures;329
1.5.6.5;18.5 Cartesian Switched Mode Architectures;333
1.5.6.6;18.6 RF Pulse Width Modulators;334
1.5.6.7;18.7 Delta-Sigma RF Pulse Width Modulation;335
1.5.6.8;18.8 Conclusions;338
1.5.6.9;References;338