E-Book, Englisch, 166 Seiten
Saini Low Power Interconnect Design
1. Auflage 2015
ISBN: 978-1-4614-1323-3
Verlag: Springer
Format: PDF
Kopierschutz: 1 - PDF Watermark
E-Book, Englisch, 166 Seiten
ISBN: 978-1-4614-1323-3
Verlag: Springer
Format: PDF
Kopierschutz: 1 - PDF Watermark
This book provides practical solutions for delay and power reduction for on-chip interconnects and buses. It provides an in depth description of the problem of signal delay and extra power consumption, possible solutions for delay and glitch removal, while considering the power reduction of the total system. Coverage focuses on use of the Schmitt Trigger as an alternative approach to buffer insertion for delay and power reduction in VLSI interconnects. In the last section of the book, various bus coding techniques are discussed to minimize delay and power in address and data buses.
