Saxena / Shelar / Sapatnekar Routing Congestion in VLSI Circuits

Estimation and Optimization
1. Auflage 2007
ISBN: 978-0-387-48550-8
Verlag: Springer US
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 250 Seiten, Web PDF

Reihe: Engineering (R0)

This volume provides the reader with a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, techniques for estimating and relieving congestion, and a critical analysis of the accuracy and effectiveness of these techniques. Readers are supplied with the knowledge to prudently choose an approach that is appropriate to their design goals. The book includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow, including the architectural level, the logic synthesis/technology mapping level, the placement phase, and the routing phase. The subjects covered include an explanation of why the problem of congestion is important and how it will trend, plus definitions of metrics that are appropriate for measuring congestion, and descriptions of techniques for estimating and optimizing routing congestion issues in cell-/library-based VLSI circuits.

Zielgruppe

Professional/practitioner

Autoren/Hrsg.

Saxena, Prashant

Shelar, Rupesh S.

Sapatnekar, Sachin

Inhaltsverzeichnis

The Origins of Congestion.- An Introduction to Routing Congestion.- The Estimation of Congestion.- Placement-level Metrics for Routing Congestion.- Synthesis-level Metrics for Routing Congestion.- The Optimization of Congestion.- Congestion Optimization During Interconnect Synthesis and Routing.- Congestion Optimization During Placement.- Congestion Optimization During Technology Mapping and Logic Synthesis.- Congestion Implications of High Level Design.