Shacham-Diamand / Osaka / Datta Advanced Nanoscale ULSI Interconnects: Fundamentals and Applications

Fundamentals and Applications
1. Auflage 2009
ISBN: 978-0-387-95868-2
Verlag: Springer-Verlag
Format: PDF
Kopierschutz: Wasserzeichen (»Systemvoraussetzungen)

E-Book, Englisch, 552 Seiten

In Advanced ULSI interconnects - fundamentals and applications we bring a comprehensive description of copper-based interconnect technology for ultra-lar- scale integration (ULSI) technology for integrated circuit (IC) application. In- grated circuit technology is the base for all modern electronics systems. You can ?nd electronics systems today everywhere: from toys and home appliances to a- planes and space shuttles. Electronics systems form the hardware that together with software are the bases of the modern information society. The rapid growth and vast exploitation of modern electronics system create a strong demand for new and improved electronic circuits as demonstrated by the amazing progress in the ?eld of ULSI technology. This progress is well described by the famous 'Moore's law' which states, in its most general form, that all the metrics that describe integrated circuit performance (e. g. , speed, number of devices, chip area) improve expon- tially as a function of time. For example, the number of components per chip d- bles every 18 months and the critical dimension on a chip has shrunk by 50% every 2 years on average in the last 30 years. This rapid growth in integrated circuits te- nology results in highly complex integrated circuits with an increasing number of interconnects on chips and between the chip and its package. The complexity of the interconnect network on chips involves an increasing number of metal lines per interconnect level, more interconnect levels, and at the same time a reduction in the interconnect line critical dimensions.

Autoren/Hrsg.

Shacham-Diamand, Yosi

Osaka, Tetsuya

Datta, Madhav

Ohba, Takayuki

Inhaltsverzeichnis

1;Preface;6
2;Acknowledgments;10
3;Contents;11
4;Contributors;15
5;Part I Introduction;19
5.1;1 Challenges in ULSI Interconnects Introduction to the Book;20
5.1.1;1.1 Material Issues in Cu Interconnects;22
5.1.2;1.2 Interconnect Performance Issues;23
5.1.3;1.3 Interconnect Process Issues;25
5.1.4;References;28
6;Part II Technology Background;29
6.1;2 MOS Device and Interconnects Scaling Physics;30
6.1.1;2.1 Device Fundamentals;30
6.1.1.1;2.1.1 The MOSFET Transistor;30
6.1.1.1.1;2.1.1.1 Basic Device Physics;30
6.1.1.1.2;2.1.1.2 Technology;32
6.1.1.2;2.1.2 Current Regimes;32
6.1.1.3;2.1.3 Mobility and Carrier Velocity;35
6.1.2;2.2 Digital Signal Propagation;36
6.1.2.1;2.2.1 Gate Delay;36
6.1.2.2;2.2.2 Gate Delay Versus Interconnect Delay;37
6.1.2.3;2.2.3 Trends in CMOS Miniaturization;38
6.1.2.3.1;2.2.3.1 Moore's Law;38
6.1.2.3.2;2.2.3.2 Roadmaps;40
6.1.2.3.3;2.2.3.3 Scaling Theory;42
6.1.2.3.4;2.2.3.4 Scaling and Power Dissipation;44
6.1.3;2.3 New Device Structures and Materials;47
6.1.3.1;2.3.1 Strained-Silicon MOSFETs;47
6.1.3.2;2.3.2 Silicon-On-Insulator (SOI);49
6.1.3.3;2.3.3 Strained Silicon and SOI;49
6.1.3.4;2.3.4 Germanium and III--V Channel Devices;50
6.1.3.5;2.3.5 Novel MOSFET Devices;51
6.1.4;References;53
6.2;3 Interconnects in ULSI Systems: Cu Interconnects Electrical Performance;54
6.2.1;3.1 Introduction;54
6.2.2;3.2 On-Chip Interconnect Requirements;54
6.2.3;3.3 Interconnect Metrics;58
6.2.4;3.4 Circuit Models of Interconnect;60
6.2.4.1;3.4.1 Ideal Interconnect;60
6.2.4.2;3.4.2 Capacitive Interconnect;61
6.2.4.3;3.4.3 Resistive Interconnect;63
6.2.4.4;3.4.4 Inductive Interconnect;65
6.2.5;3.5 The Interconnect Scaling Problem;67
6.2.6;3.6 Design Approaches and Techniques for Addressing Interconnect Problems;70
6.2.6.1;3.6.1 Metallization Stack Design;71
6.2.6.2;3.6.2 Repeater Insertion and Other Circuit Techniques;71
6.2.6.3;3.6.3 Layout Optimization Techniques;72
6.2.6.4;3.6.4 Circuit Architecture;73
6.2.7;3.7 Power Supply Interconnect;73
6.2.8;3.8 Summary;74
6.2.9;References;75
6.3;4 Electrodeposition;78
6.3.1;4.1 Introduction;78
6.3.2;4.2 Key Considerations;79
6.3.3;4.3 Pulse Plating and Pulse Reverse Plating;81
6.3.4;4.4 Electrodeposition of Copper;82
6.3.4.1;4.4.1 Electrodeposition Process for Copper Interconnects;83
6.3.5;4.5 Concluding Remarks;84
6.3.6;References;84
6.4;5 Electrophoretic Deposition;87
6.4.1;5.1 Electrophoresis and Electrophoretic Deposition;87
6.4.1.1;5.1.1 Process Limitations;87
6.4.1.2;5.1.2 Theoretical Basis;88
6.4.2;5.2 Potential Applications;88
6.4.2.1;5.2.1 Conducting Lines;89
6.4.2.2;5.2.2 Embedded Passive Components;89
6.4.2.3;5.2.3 Solid Electrolyte Capacitors;91
6.4.3;References;92
6.5;6 Wafer-Level 3D Integration for ULSI Interconnects;93
6.5.1;6.1 Introduction;93
6.5.2;6.2 Types of 3D Integration;94
6.5.3;6.3 BEOL-Based Wafer-Level 3D Processing Considerations;98
6.5.4;6.4 Wafer-Level 3D Design Opportunities;100
6.5.5;6.5 Future Projections;102
6.5.6;References;102
7;Part III Interconnect Materials;105
7.1;7 Diffusion Barriers for Ultra-Large-Scale Integrated Copper Metallization;107
7.1.1;7.1 The Motivation for the Introduction of Copper Metallization;107
7.1.2;7.2 Difficulties of Implementing Cu Metallization;108
7.1.2.1;7.2.1 Copper Diffusion Through and Degradation of the Dielectric;109
7.1.2.2;7.2.2 Copper Adhesion to the Dielectric;110
7.1.2.3;7.2.3 Copper Passivation;110
7.1.2.4;7.2.4 Copper Diffusion in and Reaction with Si;110
7.1.2.4.1;7.2.4.1 Diffusion;110
7.1.2.4.2;7.2.4.2 Precipitation;111
7.1.2.4.3;7.2.4.3 Silicides;111
7.1.2.5;7.2.5 Processing;112
7.1.3;7.3 Diffusion Barriers;112
7.1.3.1;7.3.1 Approaches and Examples;113
7.1.3.1.1;7.3.1.1 Passive Metallic Thin Films;113
7.1.3.1.2;7.3.1.2 Thermodynamically Stable Barriers;115
7.1.3.1.3;7.3.1.3 ''Stuffed'' Barriers;116
7.1.3.1.4;7.3.1.4 Sacrificial Barriers;117
7.1.3.1.5;7.3.1.5 Self-forming Barriers;118
7.1.3.1.6;7.3.1.6 Single Crystalline Barriers;118
7.1.3.1.7;7.3.1.7 Amorphous Barriers;119
7.1.3.1.8;7.3.1.8 Self-assembled Molecular Layers;119
7.1.3.2;7.3.2 Deposition Methods;120
7.1.4;7.4 Evaluation of Diffusion Barriers for Cu Metallization;121
7.1.5;7.5 Summary and Future Trends;128
7.1.6;References;130
7.2;8 Silicides;135
7.2.1;8.1 Introduction;135
7.2.2;8.2 TiSi 2 ;138
7.2.3;8.3 CoSi 2 ;139
7.2.4;8.4 NiSi;139
7.2.5;8.5 SiGe Incorporation into Silicide/Si Contacts;141
7.2.6;References;142
7.3;9 Materials for ULSI metallization -- Overview of ElectricalProperties;145
7.3.1;9.1 Introduction;145
7.3.2;9.2 Large-Grained Cu Interconnects;147
7.3.2.1;9.2.1 Abnormal Grain Growth of Cu Thin Films;147
7.3.3;9.3 Grain Growth Mechanism of Cu Thin Films;149
7.3.3.1;9.3.1 Self-formation of Nano-scale Ti Diffusion Barrier Layers in Cu(Ti) Alloy Films;152
7.3.4;9.4 Summary;154
7.3.5;References;155
7.4;10 Low-k Materials and Development Trends;158
7.4.1;10.1 Introduction;158
7.4.2;10.2 Change of Insulator Between Wiring;158
7.4.3;10.3 Low-k Materials Trends and Their Condition for Practical Usage;159
7.4.4;10.4 Technical Issues of Porous Low-k Materials and Their Provisions;160
7.4.4.1;10.4.1 Mechanical Properties;161
7.4.4.2;10.4.2 Adsorption;161
7.4.4.3;10.4.3 Heat Conduction;161
7.4.4.4;10.4.4 Relationship with Other Materials;161
7.4.5;10.5 Ultimate Porous Low-k Material;162
7.4.6;References;164
7.5;11 Electrical and Mechanical Characteristics of Air-Bridge Cu Interconnects;165
7.5.1;11.1 Introduction;165
7.5.2;11.2 Methods of Simulation;166
7.5.2.1;11.2.1 Model Structure;166
7.5.2.2;11.2.2 Electrical Simulation;168
7.5.2.3;11.2.3 Stress Simulation;169
7.5.2.4;11.2.4 Calculation of Effective Elastic Modulus, B ;172
7.5.3;11.3 Simulation Results and Discussion;172
7.5.3.1;11.3.1 Effective Dielectric Constant, keff ;172
7.5.4;11.4 Volume-Averaged Stresses;173
7.5.4.1;11.4.1 Stresses in Single-Via Structure;174
7.5.4.2;11.4.2 Stresses in Multi-Level Structure;175
7.5.4.3;11.4.3 Effective Elastic Moduli, B ;177
7.5.5;11.5 Conclusions;177
7.5.6;References;178
7.6;12 ALD Seed Layers for Plating and Electroless Plating;180
7.6.1;12.1 Introduction;180
7.6.2;12.2 Thermal and Plasma-Enhanced ALD;182
7.6.3;12.3 Palladium on Noble Metal;184
7.6.4;12.4 Palladium on Tetrasulfide Silane;184
7.6.5;12.5 Electroless Deposition of Cu on PA-ALD Pd;187
7.6.6;12.6 Conclusions;189
7.6.7;References;189
8;Part IV Deposition Processes for ULSI Interconnects;191
8.1;13 Electrochemical Processes for ULSI Interconnects;193
8.1.1;13.1 Introduction;193
8.1.2;13.2 Copper Plating Chemistry;196
8.1.2.1;13.2.1 Copper Electrodeposition for Trench Filling;196
8.1.2.1.1;13.2.1.1 Bath Composition for Void-Free Filling;196
8.1.2.1.2;13.2.1.2 Copper Deposition Mechanism and Kinetics;197
8.1.2.1.3;13.2.1.3 Chemistry of Copper Plating Bath;198
8.1.2.1.4;13.2.1.4 Reaction Mechanism: Effect of Additives;199
8.1.2.1.5;13.2.1.5 Mechanism of Void-Free Filling Effect of Additives;203
8.1.2.2;13.2.2 Copper Electroless Deposition for Trench Filling;204
8.1.2.2.1;13.2.2.1 Mechanism of Electroless Copper Deposition;205
8.1.2.2.2;13.2.2.2 Superfilling by Electroless Copper Deposition;206
8.1.3;13.3 Electrochemical Process for Seed Layer Formation;208
8.1.3.1;13.3.1 Electroless Deposition for Formation of Seed Layers;208
8.1.3.2;13.3.2 Seedless Copper Electrodeposition on Barrier Materials;209
8.1.3.3;13.3.3 Electroless Deposition for Barrier Layer Formation and Seedless Copper Filling;210
8.1.4;References;211
8.2;14 Atomic Layer Deposition (ALD) Processes for ULSIManufacturing;216
8.2.1;14.1 Introduction;216
8.2.2;14.2 Applications of Atomic Layer Deposition in ULSI Manufacturing;219
8.2.2.1;14.2.1 Front-End-of-Line (FEOL) Applications;220
8.2.2.2;14.2.2 Middle-of-Line (MOL) Applications;221
8.2.2.3;14.2.3 Back-End-of-Line (BEOL) Applications;223
8.2.3;14.3 Plasma-Assisted Atomic Layer Deposition (PAALD);226
8.2.4;14.4 Challenges for Adapting Atomic Layer Deposition in ULSI Manufacturing;226
8.2.5;References;227
8.3;15 Electroless Deposition Approaching the Molecular Scale;230
8.3.1;15.1 Introduction;230
8.3.2;15.2 Fundamentals;232
8.3.2.1;15.2.1 Steering Macroscopic Electroless Deposition;233
8.3.2.2;15.2.2 What Makes Nanoscale Deposition Special?;234
8.3.3;15.3 Scaling Down Macroscopic Electroless Deposition;235
8.3.3.1;15.3.1 Sensitization, Pd and Pd/Sn Colloids;235
8.3.3.2;15.3.2 Confinement Plating;237
8.3.3.3;15.3.3 Biomolecules as Templates;238
8.3.3.4;15.3.4 Confinement Plating in Biomolecules;240
8.3.4;References;241
9;Part V Modeling;245
9.1;16 Modeling Superconformal Electrodeposition Using an Open Source PDE Solver;246
9.1.1;16.1 Introduction;246
9.1.2;16.2 Governing Equations;249
9.1.3;16.3 Level Set Equations;252
9.1.4;16.4 Numerical Discretization;253
9.1.5;16.5 FiPy Example;256
9.1.6;16.6 Summary;259
9.1.7;References;259
10;Part VI Electrochemical Process Integration;261
10.1;17 Introduction to Electrochemical Process Integration for Cu Interconnects;263
10.1.1;17.1 Introduction;263
10.1.2;References;266
10.2;18 Damascene Concept and Process Steps;268
10.2.1;18.1 Damascene Process;268
10.2.2;18.2 Low-k Integration Challenges;271
10.2.3;18.3 Damage-Free Process;274
10.2.4;18.4 Biography;276
10.2.5;References;277
10.3;19 Advanced BEOL Technology Overview;279
10.3.1;19.1 Introduction;279
10.3.2;19.2 Low-k Materials for Each Technology Node;281
10.3.3;19.3 Metallization Issues;282
10.3.4;19.4 BEOL Technology for 90nm Technology Node;283
10.3.4.1;19.4.1 Introduction;283
10.3.4.2;19.4.2 Interconnects Structure and Low-k Film Characteristics;284
10.3.4.3;19.4.3 Dual Damascene Process;285
10.3.5;19.5 BEOL Technology for 65nm/45nm Technology Node;288
10.3.5.1;19.5.1 Introduction/Integration Issues;288
10.3.5.2;19.5.2 Application of Advanced EB Curing Process;289
10.3.6;19.6 Summary and Future Trends;294
10.3.6.1;19.6.1 Summary;294
10.3.6.2;19.6.2 Robust Process Development;295
10.3.6.3;19.6.3 Patterned Low-k Films Characterization;297
10.3.7;19.7 Biography;298
10.3.8;References;299
10.4;20 Lithography for Cu Damascene Fabrication;303
10.4.1;20.1 Introduction;303
10.4.2;20.2 Lithography Process for Cu Damascene Interconnects;303
10.4.2.1;20.2.1 Process with Photoresist (PR) Mask;306
10.4.3;20.3 Processes with Hard Masks (HM);309
10.4.4;20.4 Summary;312
10.4.5;References;313
10.5;21 Physical Vapor Deposition Barriers for Cu metallization - PVD Barriers;315
10.5.1;21.1 Necessity of Diffusion Barrier Layer;315
10.5.2;21.2 Metallurgy for Barrier Material Selection;316
10.5.3;21.3 Deposition Technique;320
10.5.4;21.4 Self-Forming Technique;321
10.5.4.1;21.4.1 Driving Force;321
10.5.4.2;21.4.2 Kinetics;324
10.5.5;References;324
10.6;22 Low-k Dielectrics;328
10.6.1;22.1 Introduction;328
10.6.2;22.2 Basic Properties of Low-k Films;330
10.6.2.1;22.2.1 Post-curing Techniques for Low-k Hardening;333
10.6.3;22.3 Innovations of Low-k Material and Process;335
10.6.4;22.4 Future Trends on CAP Dielectrics;340
10.6.5;22.5 Summary;340
10.6.6;22.6 Acknowledgments;341
10.6.7;References;342
10.7;23 CMP for Cu Processing;346
10.7.1;23.1 CMP Review;346
10.7.1.1;23.1.1 Chemical Mechanical Planarization;346
10.7.1.2;23.1.2 Application of CMP;346
10.7.2;23.2 CMP System;347
10.7.3;23.3 Cu-CMP;348
10.7.3.1;23.3.1 Application;348
10.7.3.2;23.3.2 Cu Polish Principle and Performances;351
10.7.3.3;23.3.3 Slurry Requirements;351
10.7.3.4;23.3.4 Monitors;352
10.7.3.5;23.3.5 Cleaning;353
10.7.4;23.4 General Principle of Cu-CMP;353
10.7.4.1;23.4.1 Several Planarization Technologies;354
10.7.4.2;23.4.2 CMP (Chemical Mechanical Polisher): Preston's Law;356
10.7.4.3;23.4.3 ECP (Electro Chemical Polishing): Faraday's Law;356
10.7.4.4;23.4.4 ECMP (Electrical Chemical Mechanical Polisher): Preston and Faraday's Laws;357
10.7.4.5;23.4.5 CE (Chemical Etching): Dissolution Law;358
10.7.5;23.5 General Principle of Planarization;358
10.7.6;References;359
10.8;24 Electrochemical View of Copper Chemical--MechanicalPolishing (CMP);361
10.8.1;24.1 Introduction;361
10.8.2;24.2 Ammonium Hydroxide-Based CMP Slurry;363
10.8.3;24.3 Nitric Acid (HNO 3 )-Based CMP Slurry;366
10.8.4;24.4 Peroxide-Based CMP Slurries;369
10.8.5;24.5 Carbonate- and Sorbate-Based Solutions;374
10.8.6;References;378
10.9;25 Copper Post-CMP Cleaning;381
10.9.1;25.1 Introduction;381
10.9.2;25.2 Summary;387
10.9.3;References;387
11;Part VII Electrochemical Processes and Tools;389
11.1;26 Electrochemical Processing Tools for Advanced Copper Interconnects: An Introduction;390
11.1.1;26.1 Dual Damascene Process for Electroplated Copper Interconnects;390
11.1.2;26.2 Tooling Requirements;391
11.1.3;26.3 45 nm Node and Beyond: Novel Processes and Tools;392
11.1.3.1;26.3.1 Electropolishing for Planarization;393
11.1.3.2;26.3.2 Electroless Processes for Damascene Capping;394
11.1.4;26.4 Concluding Remarks;395
11.1.5;References;396
11.2;27 Electrochemical Deposition Processes and Tools;398
11.2.1;27.1 Introduction;398
11.2.2;27.2 Electrochemical Processing Equipment;398
11.2.2.1;27.2.1 Equipment Automation and Wafer Handling;398
11.2.2.2;27.2.2 Processing Chambers;400
11.2.2.3;27.2.3 Tool Configuration;401
11.2.3;27.3 Electrochemical Processes;401
11.2.3.1;27.3.1 Damascene Copper Electrodeposition;402
11.2.3.2;27.3.2 Through-Mask Electrodeposition;406
11.2.3.3;27.3.3 Electrografting;407
11.2.3.4;27.3.4 Electrophoretic Deposition;408
11.2.4;27.4 Summary;409
11.2.5;27.5 Biographical Sketches;409
11.2.6;References;409
11.3;28 Electroless Deposition Processes and Tools;413
11.3.1;28.1 Introduction;413
11.3.2;28.2 Electroless Copper Deposition;413
11.3.2.1;28.2.1 Copper Deposition Chemistry;414
11.3.2.2;28.2.2 Electroless Copper for Seeding Barriers;416
11.3.2.3;28.2.3 Surface Activation Using Palladium;416
11.3.2.4;28.2.4 Surface Activation Through Sensitization;417
11.3.2.5;28.2.5 Direct Surface Activation Using Copper;417
11.3.2.6;28.2.6 Electroless Copper for Gap Fill;418
11.3.2.7;28.2.7 Copper Deposition Process Summary;418
11.3.3;28.3 Electroless Nickel Deposition;419
11.3.3.1;28.3.1 Nickel Deposition Chemistry;420
11.3.3.2;28.3.2 Substrate Activation;421
11.3.3.3;28.3.3 Palladium Activation of Copper Substrate;421
11.3.3.4;28.3.4 Self-Activation of Copper Substrate;422
11.3.3.5;28.3.5 Activation of Aluminum Substrates;422
11.3.3.6;28.3.6 Nickel Deposition Process Summary;425
11.3.4;28.4 Electroless Gold Deposition;425
11.3.4.1;28.4.1 Cyanide-Based Gold Deposition;425
11.3.4.2;28.4.2 Immersion Deposition;426
11.3.4.3;28.4.3 Autocatalytic Deposition;426
11.3.4.4;28.4.4 Substrate (Nickel)-Catalyzed Deposition;428
11.3.4.5;28.4.5 Non-cyanide Gold Deposition;428
11.3.5;28.5 Electroless Deposition Equipment;429
11.3.6;28.6 Biographical Sketches;430
11.3.7;References;430
11.4;29 Tools for Monitoring and Control of Bath Components;434
11.4.1;29.1 Introduction;434
11.4.2;29.2 Chemical Constituent Analysis;435
11.4.2.1;29.2.1 Titration;435
11.4.2.2;29.2.2 X-ray Fluorescence;436
11.4.2.3;29.2.3 Electroanalytical Techniques;436
11.4.2.3.1;29.2.3.1 Cyclic Voltammetric Stripping;436
11.4.2.3.2;29.2.3.2 CPVS;437
11.4.2.3.3;29.2.3.3 PCGA;438
11.4.2.3.4;29.2.3.4 Chronoamperometry;438
11.4.2.4;29.2.4 Photometric Techniques;439
11.4.2.5;29.2.5 Probes and Electrodes;439
11.4.2.6;29.2.6 Liquid Chromatography;439
11.4.2.7;29.2.7 Mass Spectrometry;440
11.4.2.8;29.2.8 Analytical Techniques Summary;440
11.4.3;29.3 Constituent Replenishment;441
11.4.4;29.4 System Design;441
11.4.5;29.5 Biographical Sketches;442
11.4.6;References;443
11.5;30 Processes and Tools for Co Alloy Capping;444
11.5.1;30.1 Introduction;444
11.5.2;30.2 Co Alloy Capping Applications;444
11.5.3;30.3 Film Properties and Requirements;446
11.5.4;30.4 Process Sequence and Integration;448
11.5.5;30.5 Deposition Chemistry;449
11.5.6;30.6 Co Alloy Capping System;450
11.5.7;30.7 Conclusion;454
11.5.8;References;454
11.6;31 Advanced Planarization Techniques;457
11.6.1;31.1 Introduction;457
11.6.2;31.2 Electrochemical Polishing;458
11.6.2.1;31.2.1 Conventional Copper Electropolishing Processes;458
11.6.3;31.3 Novel Electropolishing Approaches;459
11.6.4;31.4 Electrochemical Mechanical Deposition;460
11.6.4.1;31.4.1 Planarization Mechanism of ECMD;461
11.6.5;31.5 ElectroChemical Mechanical Planarization (ECMP);467
11.6.5.1;31.5.1 Planarization Mechanism of ECMP;467
11.6.6;References;470
12;Part VIII Metrology;474
12.1;32 Integrated Metrology (IM) History at a Glance;475
12.1.1;32.1 Introduction;475
12.1.2;32.2 Integrated Metrology (IM) Technology;477
12.1.3;32.3 IM CLC;481
12.1.4;32.4 CLC Results;484
12.1.5;32.5 Qualitative View for ITM Return on Investment;484
12.1.5.1;32.5.1 Capital Investment;486
12.1.5.2;32.5.2 Labor Reduction;486
12.1.5.3;32.5.3 Process;487
12.1.5.3.1;32.5.3.1 Rework;487
12.1.5.3.2;32.5.3.2 Reduction of Test Wafer Usage;487
12.1.5.3.3;32.5.3.3 Excursion Detection;487
12.1.5.3.4;32.5.3.4 Yield;487
12.1.6;32.6 Manufacturing;487
12.1.6.1;32.6.1 Cycle Time Reduction;487
12.1.6.2;32.6.2 Reduced Downtime After PM and Faster Tool Qualification;488
12.1.7;32.7 Shallow Trench Isolation (STI);488
12.1.8;32.8 Pre-metal Dielectric (PMD);488
12.1.9;32.9 Copper;489
12.1.10;32.10 Future Considerations;489
12.1.11;32.11 Summary;490
12.1.12;References;490
12.2;33 Thin Film Metrology X-ray Methods;492
12.2.1;33.1 X-Ray Fluorescence (XRF);492
12.2.2;33.2 X-Ray Reflectometry (XRR);493
12.2.3;33.3 Small-Angle X-Ray Scattering (SAXS);495
13;Part IX Summary and Foresight;498
13.1;34 Emerging Nanoscale Interconnect Processing Technologies: Fundamental and Practice;499
13.1.1;34.1 Introduction;499
13.1.2;34.2 Nanoscale Copper Interconnect Architectures;500
13.1.2.1;34.2.1 Hyper-integration Interconnects;502
13.1.2.2;34.2.2 Die-to-Die Integration;503
13.1.2.3;34.2.3 Die-to-Wafer Integration;503
13.1.2.4;34.2.4 Wafer-to-Wafer Integration;504
13.1.3;34.3 Nanoscale Interconnects Technology: Moletronics;505
13.1.3.1;34.3.1 Carbon Nanotubes;506
13.1.3.2;34.3.2 Geometric and Electronic Structures of CNTs;508
13.1.3.3;34.3.3 Mechanical and Thermal Properties of CNTs;509
13.1.3.4;34.3.4 Interconnect Applications of CNTs;510
13.1.3.4.1;34.3.4.1 Tube-Tube Junctions;510
13.1.3.4.2;34.3.4.2 Tube--Metal Contacts;512
13.1.3.5;34.3.5 Alternatives Molecular Systems;513
13.1.3.5.1;34.3.5.1 Charge Transport Mechanisms;513
13.1.3.5.2;34.3.5.2 Self-assembly Techniques;514
13.1.3.6;34.3.6 Self-assembly Techniques;516
13.1.4;34.4 Nanoscale Interconnects Technology: Spintronics;516
13.1.5;34.5 Prolog: Electroplating as Enabling Technology;518
13.1.6;34.6 Conclusions;520
13.1.7;References;520
13.2;35 Self-Assembly of Short Aromatic Peptides: From Amyloid Fibril Formation to Nanotechnology;525
13.2.1;35.1 The Formation of Nanostructures by Short Aromatic Peptides;525
13.2.1.1;35.1.1 Bio-inspired Biological Nano-assemblies;525
13.2.1.2;35.1.2 The Role of Aromatic Residues in the Self-Assembly of Amyloid Nano-fibrils;525
13.2.1.3;35.1.3 The Identification of Aromatic Dipeptide Nanotubes (ADNT);527
13.2.2;35.2 Technological Applications of the Peptide Tubes;528
13.2.3;35.3 The Formation of Nano-spheres by Related Aromatic Dipeptides;529
13.2.4;35.4 Other Modified Aromatic Homo-dipeptides;529
13.2.5;35.5 The Technological Advantages of Peptide Building Blocks;530
13.2.6;35.6 Summary;530
13.2.7;References;531
14;Index;532