Shankar / Fernandez / Einspruch VLSI and Computer Architecture

1. Auflage 2014
ISBN: 978-1-4832-1784-0
Verlag: Elsevier Science & Techn.
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, Band Volume 20, 502 Seiten, Web PDF

Reihe: VLSI Electronics Microstructure Science

VLSI Electronics Microstructure Science, Volume 20: VLSI and Computer Architecture reviews the approaches in design principles and techniques and the architecture for computer systems implemented in VLSI. This volume is divided into two parts. The first section is concerned with system design. Chapters under this section focus on the discussion of such topics as the evolution of VLSI; system performance and processor design considerations; and VLSI system design and processing tools. Part II of the book focuses on the architectural possibilities that have become cost effective with the development of VLSI circuits. Topics on architectural requirements and various architectures such as the Reduced Instruction Set, Extended Von Neumann, Language-Oriented, and Microprogrammable architectures are elaborated in detail. Also included are chapters that discuss the evaluation of architecture, multiprocessing configurations, and the future of VLSI. Computer designers, those evaluating computer systems, researchers, and students of computer architecture will find the book very useful.

Autoren/Hrsg.

Shankar, Ravi

Fernandez, Eduardo B.

Einspruch, Norman G.

Inhaltsverzeichnis

1;Front Cover;1
2;VLSI and Computer Architecture;4
3;Copyright Page;5
4;Table of Contents;6
5;Preface to Part I;12
6;Preface to Part II;14
7;Part I: SYSTEM DESIGN;16
7.1;Chapter 1. An Introduction to VLSI;18
7.1.1;1.1. THE EVOLUTION OF DIGITAL ELECTRONICS TOWARD VLSI AND BEYOND;18
7.1.2;1.2. A COMPARISON OF DIFFERENT VLSI TECHNOLOGIES;27
7.2;Chapter 2. Silicon MOS Technology;32
7.2.1;2.1. INTRODUCTION;32
7.2.2;2.2. DEVICE CHARACTERISTICS;35
7.2.3;2.3. LOGIC FAMILIES;41
7.2.4;2.4. MEMORY ELEMENTS;64
7.2.5;2.5. FABRICATION;74
7.2.6;2.6. SCALING AND DESIGN RULES;80
7.2.7;2.7. SCALING CONSTRAINTS AND VLSI TRENDS;81
7.2.8;2.8. SYSTEM PERFORMANCE CONSIDERATIONS;93
7.2.9;2.9. PROCESSOR DESIGN CONSIDERATIONS;99
7.3;Chapter 3. Silicon Bipolar Integrated Circuits;112
7.3.1;3.1. INTRODUCTION;112
7.3.2;3.2. LOGIC FAMILIES;112
7.3.3;3.3. MEMORY ELEMENTS;120
7.3.4;3.4. FABRICATION;125
7.3.5;3.5. SYSTEM PERFORMANCE CONSIDERATIONS;126
7.3.6;3.6. PROCESSOR DESIGN CONSIDERATIONS;133
7.3.7;3.7. BIPOLAR TRENDS;135
7.4;Chapter 4. Gallium-Arsenide Technology;140
7.4.1;4.1. INTRODUCTION;140
7.4.2;4.2. DEVICES;143
7.4.3;4.3. FABRICATION;145
7.4.4;4.4. LOGIC FAMILIES;147
7.4.5;4.5. SYSTEM PERFORMANCE CONSIDERATIONS;149
7.4.6;4.6. PROCESSOR DESIGN CONSIDERATIONS;155
7.5;Chapter 5. Superconductive Electronics;162
7.5.1;5.1. INTRODUCTION;162
7.5.2;5.2. DEVICES;165
7.5.3;5.3. FABRICATION;167
7.5.4;5.4. LOGIC FAMILIES;169
7.5.5;5.5. MEMORY ELEMENTS;173
7.5.6;5.6. SYSTEM PERFORMANCE CONSIDERATIONS;174
7.5.7;5.7. PROCESSOR DESIGN CONSIDERATIONS;177
7.6;Chapter 6. An Overview of Digital VLSI System Design;180
7.6.1;6.1. INTRODUCTION;180
7.6.2;6.2. DESIGN METHODOLOGIES;186
7.6.3;6.3. DESIGN AIDS AND TOOLS;188
7.6.4;6.4. DESIGN STYLES;194
7.6.5;6.5. COMPARISON OF DIFFERENT DESIGN STYLES;204
7.6.6;6.6. CURRENT RESEARCH AND DEVELOPMENT EFFORTS;208
7.7;Chapter 7. Design Automation Tools;212
7.7.1;7.1. INTRODUCTION;212
7.7.2;7.2. STANDARD INTERFACES;217
7.7.3;7.3. LOGIC SYNTHESIS AND OPTIMIZATION;232
7.7.4;7.4. PLACEMENT AND ROUTING;239
7.7.5;7.5. TESTING;260
7.7.6;7.6. SILICON COMPILERS;270
7.8;Chapter 8. Examples of CAD Systems and VLSI Designs;276
7.8.1;8.1. INTRODUCTION;276
7.8.2;8.2. BIPOLAR SYSTEMS;276
7.8.3;8.3. MOS SYSTEMS: UNIVERSITY-BASED DESIGNS;277
7.8.4;8.4. MOS SYSTEMS: COMMERCIAL DESIGNS;281
7.8.5;8.5. GALLIUM-ARSENIDE SYSTEMS;306
7.8.6;8.6. SUPERCONDUCTING SYSTEMS;312
7.9;Chapter 9. VLSI Trends;314
7.9.1;9.1. FABRICATION;314
7.9.2;9.2. VERY HIGH SPEED INTEGRATED CIRCUITS;318
7.9.3;9.3. TESTABILITY AND TESTING;320
7.9.4;9.4. THREE-DIMENSIONAL INTEGRATED CIRCUITS;334
7.9.5;9.5. FAULT TOLERANCE TECHNIQUES AND YIELD;338
7.9.6;9.6. PACKAGING;343
7.9.7;9.7. INTEGRATION OF ANALOG FUNCTIONS;347
7.9.8;References;356
8;Part II: Architectural Aspects;370
8.1;Chapter 10. Introduction;372
8.1.1;10.1. MOTIVATION;372
8.1.2;10.2. VLSI AS AN IMPLEMENTATION MEDIUM;373
8.1.3;10.3. ADVANCES;375
8.1.4;10-4. OVERVIEW OF PART II;376
8.2;Chapter 11. Architectural Requirements;378
8.2.1;11.1. GENERAL OBJECTIVES OF AN ARCHITECTURE;378
8.2.2;11.2. INSTRUCTION SET ARCHITECTURE;378
8.2.3;11.3. MICROARCHITECTURE;380
8.2.4;11.4. SUPPORT FOR DATA STRUCTURES AND DATA TYPES;381
8.2.5;11.5. SUPPORT FOR SUBROUTINE CALLS;381
8.2.6;11.6. MEMORY MANAGEMENT;382
8.2.7;11.7. VIRTUAL MACHINES;383
8.2.8;11.8. SUPPORT FOR MULTIPROCESSING;383
8.2.9;11.9. WORD LENGTH;384
8.2.10;11.10. INDEPENDENCE OF DATA AND CONTROL UNITS;384
8.2.11;11.11. SECURITY AND RELIABILITY;385
8.2.12;11.12. PERFORMANCE;386
8.3;Chapter 12. Reduced Instruction Set Architectures;388
8.3.1;12.1. ADVANTAGES OF SIMPLER INSTRUCTION SETS;388
8.3.2;12.2. EXAMPLES;389
8.4;Chapter 13. Extended Von Neumann Architectures;400
8.4.1;13.1. COMPLEX INSTRUCTION SETS;400
8.4.2;13.2. EXAMPLES;401
8.5;Chapter 14. Security-Oriented Architectures;412
8.5.1;14.1. ENHANCING SECURITY;412
8.5.2;14.2. EXAMPLES;412
8.6;Chapter 15. Harvard Architectures;420
8.6.1;15.1. SEPARATION OF INSTRUCTIONS FROM DATA;420
8.7;Chapter 16. Language-Oriented Architectures;424
8.7.1;16.1. SUPPORT OF HIGH-LEVEL LANGUAGES;424
8.7.2;16.2. EXAMPLES;425
8.8;Chapter 17. Object-Oriented Architectures;432
8.8.1;17.1. OBJECTS AT THE ARCHITECTURAL LEVEL;432
8.8.2;17.2. EXAMPLES;433
8.9;Chapter 18. Microprogrammable Architectures;438
8.9.1;18.1. MICROINSTRUCTION SETS;438
8.9.2;18.2. EXAMPLE: NCR/32;438
8.10;Chapter 19. Architectural Evaluation;442
8.10.1;19.1. HOW TO EVALUATE ARCHITECTURES;442
8.10.2;19.2. INSTRUCTION SET ARCHITECTURE;442
8.10.3;19.3. MICROARCHITECTURE;444
8.10.4;19.4. COMPACT CODE REPRESENTATION;447
8.10.5;19.5. SUPPORT FOR DATA STRUCTURES AND DATA TYPES;447
8.10.6;19.6. SUPPORT FOR SUBROUTINE CALLS;448
8.10.7;19.7. SUPPORT FOR PROGRAM MODULARITY;448
8.10.8;19.8. SUPPORT OF PROCESS SWITCHING;449
8.10.9;19.9. SUPPORT FOR MEMORY HIERARCHIES;450
8.10.10;19.10. SUPPORT FOR VIRTUAL MACHINES;452
8.10.11;19.11. SUPPORT FOR MULTIPROCESSING;452
8.10.12;19.12. COMPILER ASPECTS;453
8.10.13;19.13. SECURITY;453
8.10.14;19,14. RELIABILITY;456
8.10.15;19.15. PIPELINING;457
8.10.16;19.16. PERFORMANCE;457
8.11;Chapter 20. VLSI and Multiprocessing;460
8.11.1;20.1. APPROACHES TO MULTIPROCESSING;460
8.11.2;20.2. EXAMPLES;461
8.12;Chapter 21. Applications;466
8.12.1;21.1. SUMMARY OF FEATURES;466
8.12.2;21.2. TYPES OF APPLICATION FOR VLSI CHIPS;466
8.12.3;21.3. TYPICAL APPLICATIONS;469
8.13;Chapter 22. The Future;472
8.13.1;22.1. A DIFFERENT APPROACH TO DESIGN;472
8.13.2;22.2. BETTER DESIGN AND TESTING;472
8.13.3;22.3. WAFER-SCALE INTEGRATION;473
8.13.4;22.4. PARALLEL ARCHITECTURES;473
8.13.5;22.5. NEW TECHNOLOGIES;474
9;References;475
10;Index;486