Shibkov ESD Design for Analog Circuits

1. Auflage 2010
ISBN: 978-1-4419-6565-3
Verlag: Springer-Verlag
Format: PDF
Kopierschutz: Adobe DRM (»Systemvoraussetzungen)

E-Book, Englisch, 459 Seiten

This Book and Simulation Software Bundle Project Dear Reader, this book project brings to you a unique study tool for ESD protection solutions used in analog-integrated circuit (IC) design. Quick-start learning is combined with in-depth understanding for the whole spectrum of cro- disciplinary knowledge required to excel in the ESD ?eld. The chapters cover technical material from elementary semiconductor structure and device levels up to complex analog circuit design examples and case studies. The book project provides two different options for learning the material. The printed material can be studied as any regular technical textbook. At the same time, another option adds parallel exercise using the trial version of a complementary commercial simulation tool with prepared simulation examples. Combination of the textbook material with numerical simulation experience presents a unique opportunity to gain a level of expertise that is hard to achieve otherwise. The book is bundled with simpli?ed trial version of commercial mixed- TM mode simulation software from Angstrom Design Automation. The DECIMM (Device Circuit Mixed-Mode) simulator tool and complementary to the book s- ulation examples can be downloaded from www.analogesd.com. The simulation examples prepared by the authors support the speci?c examples discussed across the book chapters. A key idea behind this project is to provide an opportunity to not only study the book material but also gain a much deeper understanding of the subject by direct experience through practical simulation examples.

Autoren/Hrsg.

Shibkov, Andrei

Inhaltsverzeichnis

1;Preface;6
1.1;This Book and Simulation Software Bundle Project;6
1.2;Subject and Purpose of This Book;7
1.3;The Book Structure;8
2;Acknowledgments;11
3;Contents;13
4;1 Introduction;19
4.1;1.1 Analog and Digital in Prism of ESD Design;19
4.2;1.2 Important Definitions;22
4.2.1;1.2.1 ESD Protection Network;22
4.2.2;1.2.2 ESD Clamps;24
4.2.3;1.2.3 Absolute Maximum Limits and Pulsed SOA;25
4.2.4;1.2.4 ESD Pulse Specification;26
4.2.5;1.2.5 Breakdown and Instability;27
4.3;DECIMM TM Simulation Examples for Introduction ;32
5;2 Conductivity Modulation in Semiconductor Structures Under Breakdown and Injection;33
5.1;2.1 Important Definitions and Limitations;33
5.1.1;2.1.1 Basic Semiconductor Structures;33
5.1.2;2.1.2 Conductivity Modulation and Negative Differential Resistance;35
5.1.3;2.1.3 Spatial Current Instability, Filamentation, and Suppression;36
5.1.4;2.1.4 Snapback Operation;38
5.1.5;2.1.5 Notes to the Methodology of Material Presentation in This Chapter;40
5.2;2.2 Avalanche Breakdown in Reverse-Biased pn Structure;41
5.2.1;2.2.1 Analytical Description of the Avalanche Breakdown Phenomenon;42
5.2.2;2.2.2 Numerical Analysis of the Avalanche Breakdown in the p + 0p0n + Structure p + -p-n + structure ;44
5.3;2.3 Double-AvalancheInjection in pin Structures;48
5.3.1;2.3.1 An Analytical Description of the Effect;48
5.3.2;2.3.2 Numerical Analysis for the p--i--n Diode Structure;49
5.4;2.4 AvalancheInjection in Si n + nn + Diode Structure;51
5.4.1;2.4.1 Analytical Approach;52
5.4.2;2.4.2 Simulation Analysis;54
5.5;2.5 Conductivity Modulation Instability in npn Diode Structures;55
5.5.1;2.5.1 Conductivity Modulation in a Floating Base Region: Diode Operation Mode;55
5.5.1.1;2.5.1.1 The Case of Floating Base Breakdown (BVCEO) I B = 0;55
5.5.1.2;2.5.1.2 Numerical Solution for I B = 0 Case;57
5.6;2.6 Conductivity Modulation in the Triode npn Structure;58
5.6.1;2.6.1 The Case of Grounded Base Breakdown Operation U EB = 0 (BVCES);58
5.6.2;2.6.2 The Floating Emitter Case I E =0;59
5.6.3;2.6.3 Avalanche-Injection in a Common Emitter Circuit: The Case of I B< 0 Regime;59
5.6.3.1;2.6.3.1 Numerical Analysis for I B < 0 Case;62
5.6.4;2.6.4 Avalanche-Injection in the Common Emitter Circuit with Positive Base Current IB> 0;65
5.6.4.1;2.6.4.1 Analytical Description of the I B > 0 Case;66
5.6.4.2;2.6.4.2 Numerical Analysis of the I B > 0 Case;67
5.6.5;2.6.5 Avalanche--Injection in the Common Base Circuit;69
5.7;2.7 AvalancheInjection in PNP Structures;70
5.8;2.8 Double Injection in Si pnpn Structures;71
5.8.1;2.8.1 Equivalent Circuit;71
5.8.2;2.8.2 Simulation of Conductivity Modulation in p--n--p--n Structures;74
5.8.2.1;2.8.2.1 Floating Base Case;74
5.8.2.2;2.8.2.2 Connected Base Case;76
5.9;2.9 Spatial Current Instability Phenomena in Semiconductor Structures with Negative Differential Resistance;77
5.9.1;2.9.1 Current Filamentation at Avalanche--Injection;78
5.9.2;2.9.2 Current Filamentation Effect in Double-Avalanche--Injection Conductivity Modulation;81
5.9.3;2.9.3 Current Filamentation Effect in the Case of Double Injection;84
5.10;2.10 Summary;84
5.11;DECIMM TM Simulation Examples DECIMM TM Simulation examples for Chapter 2 ;86
6;3 Standard and ESD Devices in Integrated Process Technologies;87
6.1;3.1 ESD Specifics in Integrated Process Technology;88
6.1.1;3.1.1 Typical DGO CMOS Process with Extended Voltage Components;88
6.1.1.1;3.1.1.1 Initial Wafer Material;89
6.1.1.2;3.1.1.2 Device Isolation;90
6.1.1.3;3.1.1.3 Deep Nwell isolation;91
6.1.1.4;3.1.1.4 Well Implants;93
6.1.1.5;3.1.1.5 Gate Oxide;94
6.1.1.6;3.1.1.6 Polygate;94
6.1.1.7;3.1.1.7 Lightly Doped Drain Implants;96
6.1.1.8;3.1.1.8 Spacer Formation and NPLUS and PPLUS Implants;97
6.1.1.9;3.1.1.9 Activation and Silicidation;98
6.1.1.10;3.1.1.10 Contacts and Backend;100
6.1.2;3.1.2 ESD Specific for BCD and BiCMOS Integrated Process Flow;101
6.1.2.1;3.1.2.1 Generic Process Flow;101
6.1.2.2;3.1.2.2 Subcollector and Substrate Isolation Regions;102
6.1.2.3;3.1.2.3 Isolation BCD Process Steps;104
6.1.2.4;3.1.2.4 Collector and Initial CMOS Regions;104
6.2;3.2 Safe Operating Area in ESD Pulse Regime;105
6.2.1;3.2.1 SOA and Current Instability Boundary in Reliability;106
6.2.2;3.2.2 Pulsed SOA for ESD Regimes;108
6.2.2.1;3.2.2.1 Standard Devices;109
6.2.3;3.2.3 ESD SOA for Typical Devices in BCD Process;110
6.2.3.1;3.2.3.1 Waveform SOA Measurements;113
6.2.4;3.2.4 Instability Boundary and SOA for ESD devices;114
6.2.5;3.2.5 Physical Limitation of ESD Devices. Spatial Thermal Runaway;116
6.3;3.3 Low-Voltage ESD Devices in CMOS Processes;120
6.3.1;3.3.1 Snapback NMOS;121
6.3.1.1;3.3.1.1 Three-Dimensional Simulation of Current Instability in Snapback NMOS Devices;122
6.3.2;3.3.2 FOX (TFO) ESD device;123
6.3.2.1;3.3.2.1 Surface NPN;125
6.3.3;3.3.3 LVTSCR and FOXSCR;127
6.3.4;3.3.4 Low-Voltage Avalanche Diodes;129
6.3.4.1;3.3.4.1 Comparison of the Surface and Buried Avalanche Diodes;130
6.4;3.4 ESD Devices in BJT Processes;130
6.4.1;3.4.1 Integrated NPN BJT Devices;132
6.4.2;3.4.2 Bipolar SCR;134
6.5;3.5 High-Voltage ESD Devices in BCD and Extended Voltage CMOS Processes;135
6.5.1;3.5.1 LDMOS-SCR and DeMOS-SCR Devices;136
6.5.2;3.5.2 Lateral PNP BJT Devices;139
6.5.3;3.5.3 High-Voltage Avalanche Diodes;144
6.6;3.6 Dual Direction Devices;145
6.6.1;3.6.1 Dual-Direction Device Architecture in CMOS Process;146
6.6.1.1;3.6.1.1 Device-Level Positive and Negative Feedback;147
6.6.2;3.6.2 High-Voltage Dual-Direction Devices;149
6.6.3;3.6.3 Dual Direction ESD Devices Based upon Si--Ge NPN BJT Structure;152
6.6.3.1;3.6.3.1 Experimental Characteristics of the DD-BJT Cl155
6.7;3.7 ESD Diodes and Passive Components;157
6.7.1;3.7.1 Forward-Biased ESD Diodes;157
6.7.1.1;3.7.1.1 CMOS Diodes CMOS diodes ;158
6.7.1.2;3.7.1.2 Gated Diodes Gated diodes ;159
6.7.2;3.7.2 Passives;160
6.7.2.1;3.7.2.1 Saturation Resistors Saturation resistors [ 59 ];161
6.7.2.2;3.7.2.2 Thin Film Resistors;164
6.8;3.8 Summary;165
6.9;DECIMM TM Simulation Examples for Chapter 3 ;166
6.9.1;Example 3.1 Standard Devices in BCD Process Technology;167
6.9.2;Example 3.2 Typical ESD Devices in 0.5 m BCD Process Technology;168
6.9.3;Example 3.3 Ring Oscillators;171
7;4 ESD Clamps;173
7.1;4.1 Active NMOS Cl176
7.2;4.2 Low-Voltage Clamps with Internal Blocking Junction Reference or d V /d t Turn-on;179
7.2.1;4.2.1 Snapback NMOS Clamps;179
7.2.1.1;4.2.1.1 Ground-Referenced Snapback NMOS;179
7.2.1.2;4.2.1.2 Gate Coupling;179
7.2.1.3;4.2.1.3 Displacement Current Effect;180
7.2.1.4;4.2.1.4 Reverse Path Protection;182
7.2.1.5;4.2.1.5 Isolated Snapback NMOS Isolated Snapback NMOS ;182
7.2.1.6;4.2.1.6 The 40 Rule for Backend;184
7.2.2;4.2.2 Transient-Triggered PMOS Cl185
7.2.3;4.2.3 100V FOX Snapback Device FOX Snapback device ;187
7.2.4;4.2.4 LVTSCR and FOX-SCR Clamps;189
7.2.5;4.2.5 High Holding Voltage LVTSCR Clamps;190
7.2.5.1;4.2.5.1 High Holding Voltage Cell Topology;190
7.2.5.2;4.2.5.2 Clamp-Level High Holding Voltage Using P-Emitter De-biasing;192
7.2.6;4.2.6 Triggering Characteristics Control in SCR Clamps;194
7.2.6.1;4.2.6.1 Mixed Device-Circuit Concept;195
7.2.6.2;4.2.6.2 Practical Implementation of the Concept for the Case of 130 nm Process ;195
7.2.6.3;4.2.6.3 Principle of Dual-Base Control Operation;196
7.2.6.4;4.2.6.4 Pulsed Characterization of Dual-Base Control (DBC) Cl198
7.2.6.5;4.2.6.5 DC Leakage of DBC Cl199
7.3;4.3 Voltage and Current Reference in ESD Cl200
7.3.1;4.3.1 Low-Voltage Clamps in BiCMOS process technology;201
7.3.2;4.3.2 NPN Clamps with Voltage Reference;203
7.4;4.4 High-Voltage ESD Devices;206
7.4.1;4.4.1 20 V NPN with Blocking Junction Internal Reference;207
7.4.2;4.4.2 NPN Clamp with External Lateral Avalanche Diode Reference;208
7.4.3;4.4.3 SCR-Based High-Voltage Cl208
7.4.4;4.4.4 Lateral LPNP Cl208
7.4.5;4.4.5 Mixed Device-Circuit Dual Mode Solutions;209
7.4.5.1;4.4.5.1 Example of Circuit Design;210
7.5;4.5 The Concept of Self-Protection;214
7.5.1;4.5.1 Device-Level Self-Protection;214
7.5.2;4.5.2 Array-Level Protection;216
7.6;4.6 ESD Protection of Ultra High Voltage Circuits;218
7.7;4.7 Summary;221
7.8;DECIMMTM Simulation Examples for Chapter 4;222
7.8.1;Example 4.1 Snapback NMOS Clamp Operation Analysis;222
7.8.2;Example 4.2 LVTSCR ESD Clamps;223
7.8.3;Example 4.3 Two-Stage ESD Protection with Snapback NMOS;224
7.8.4;Example 4.4 High-Voltage NLDMOS-SCR Clamp with High-Side Avalanche Diode Reference;225
7.8.5;Example 4.5 PNP Clamp with Low Side Avalanche Diode Reference;226
7.8.6;Example 4.6 High-Voltage NPN Cl227
7.8.7;Example 4.7 Bipolar SCR ESD Cl228
7.8.8;Example 4.8 Diode-Triggered SCR ESD Cl229
8;5 ESD Network Design Principles;231
8.1;5.1 Rail-Based ESD Protection Network;233
8.1.1;5.1.1 Rail Based and Local ESD Protection;233
8.1.2;5.1.2 Rail-Based ESD Protection Using Snapback Clamps;235
8.1.3;5.1.3 Rail-Based ESD Protection Using Active Clamps;237
8.1.4;5.1.4 Specific of Active Clamp Design in BiCMOS Processes;241
8.1.4.1;5.1.4.1 Verification by Circuit Simulation;241
8.1.4.2;5.1.4.2 Experimental Comparison;243
8.1.4.3;5.1.4.3 Active Clamp Protection in Complementary BiCMOS with Low-Voltage CMOS Components;245
8.1.5;5.1.5 Bipolar Differential Input Protection;250
8.1.6;5.1.6 Bipolar Output Protection;252
8.1.7;5.1.7 CMOS Input and Output Protection;253
8.1.8;5.1.8 Array-Level Consideration;255
8.1.9;5.1.9 Concept of Two-Stage Protection;258
8.1.9.1;5.1.9.1 CMOS Input CMOS Input ;258
8.1.9.2;5.1.9.2 Diode-Based Compact Two-Stage ESD Protection Circuit;259
8.1.9.3;5.1.9.3 Two-Stage ESD Protection Circuit for BJT Base;261
8.1.9.4;5.1.9.4 Two-Stage Network with Snapback NMOS;262
8.2;5.2 Local Clamp-Based ESD Protection Network;265
8.2.1;5.2.1 Local ESD Protection;265
8.2.2;5.2.2 Serial Data Line Pin Case Study;266
8.2.3;5.2.3 Erase Pin Protection in EEPROM;268
8.2.4;5.2.4 Local Protection of the Internal Pins;271
8.2.5;5.2.5 Local Protection of the High-Speed I/O pins;274
8.3;5.3 ESD Network for Multiple Voltage Domains;276
8.3.1;5.3.1 Multiple Voltage Domains;276
8.3.2;5.3.2 Protection of Multiple Voltage Domains with Single Active Clamp Network;278
8.3.3;5.3.3 Local Bi-directional ESD Protection of Differential Input;279
8.4;5.4 ESD Network Simulation with ESD Compact Models;281
8.4.1;5.4.1 Compact Model for Snapback NMOS and PMOS Devices;281
8.4.2;5.4.2 Snapback LVTSCR Model;283
8.4.3;5.4.3 Extended Voltage Snapback Compact Models;283
8.4.4;5.4.4 High-Voltage Open Drain Circuit Analysis;288
8.5;5.5 Summary;290
8.6;DECIMM TM Simulation Examples for Chapter 5 ;290
8.6.1;Example 5.1 Active 5 V NMOS Cl290
8.6.2;Example 5.2 Active 5 V PMOS Cl291
8.6.3;Example 5.3 EEPROM Erase pin Protection;292
8.6.4;Example 5.4 BJT-Based Active Clamps;293
8.6.5;Example 5.5 Stacked Active Clamps for High Voltage Tolerance;295
8.6.6;Example 5.6 Stacked Active Clamps with NPN;296
8.6.7;Example 5.7 Stacked Active Clamps with PNP;297
9;6 ESD Design for Signal Path Analog;298
9.1;6.1 Amplifiers;299
9.1.1;6.1.1 Amplifier Product Families and Specifications;299
9.1.2;6.1.2 ESD Solutions for Amplifiers;305
9.1.3;6.1.3 Bipolar Output High-Voltage Audio Amplifiers;307
9.1.4;6.1.4 Bipolar Output Protection in Low-Voltage Amplifiers;309
9.1.5;6.1.5 Input Protection;310
9.1.6;6.1.6 CMOS Output;312
9.2;6.2 Digital-to-Analog and Analog-to-Digital Converters;313
9.2.1;6.2.1 Functional Blocks for High-Speed DAC;314
9.2.1.1;6.2.1.1 ESD Protection Network;316
9.3;6.3 High-Speed Interface IO pins;318
9.3.1;6.3.1 Interface Analog Products;318
9.3.2;6.3.2 Cable Discharge Event Test Procedure for Integrated Circuits;319
9.3.3;6.3.3 ESD Protection of Interface Pins with CDE Requirements;322
9.4;6.4 Summary;324
9.5;DECIMMTM Simulation Examples for Chapter 6 ;324
9.5.1;Example 6.1a 6.1c Rail-Based Protection with Active 5 V NMOS Clamp and ESD Diodes;325
9.5.2;Example 6.2 Rail-Based Protection with 5 V Snapback NMOS Clamp and ESD Diodes;327
9.5.3;Example 6.3 Trans Impedance Amplifier;329
9.5.4;Example 6.4 CMOS Output Stage ESD Case;329
9.5.5;Example 6.5 CMOS Open Drain Case;330
9.5.6;Example 6.6 BJT Output Stage Case;331
10;7 Power Management Circuits ESD Protection;333
10.1;7.1 Power Management Products;334
10.1.1;7.1.1 Power Management Products and ESD Challenges;334
10.1.1.1;7.1.1.1 Market Trends;334
10.1.1.2;7.1.1.2 ESD Challenges;335
10.1.2;7.1.2 Integrated DC--DC Converters and Controllers;337
10.1.3;7.1.3 Integrated Power Arrays;339
10.1.3.1;7.1.3.1 Power Losses;339
10.1.3.2;7.1.3.2 Self-Protection Capability (SPC) of Integrated Power Arrays;344
10.1.3.3;7.1.3.3 Physical Simulation of DeMOS Power Arrays in ESD Regime;350
10.2;7.2 Low-Voltage Power Circuit ESD Cases;354
10.2.1;7.2.1 LV Power Switching Blocks;354
10.2.2;7.2.2 Step-Down DC--DC Converters;356
10.2.3;7.2.3 Local Snapback Protection of LV Switch Pin;359
10.2.3.1;7.2.3.1 Case Study;359
10.2.3.2;7.2.3.2 Mixed-Mode Simulation;361
10.3;7.3 ESD Protection of Integrated High-Voltage Regulators;363
10.3.1;7.3.1 Asynchronous Integrated Buck Regulator Case;363
10.3.1.1;7.3.1.1 Functionality and ESD Protection;363
10.3.1.2;7.3.1.2 Case Study;365
10.3.2;7.3.2 Synchronous Regulators;367
10.3.2.1;7.3.2.1 HV Power Train Block;367
10.3.2.2;7.3.2.2 Synchronous Buck Regulator;369
10.4;7.4 Controllers;373
10.4.1;7.4.1 Asynchronous Buck-Boost (SEPIC) Controller;375
10.4.2;7.4.2 Synchronous Buck Controller;378
10.5;7.5 Light Management Units and LED Drivers;380
10.5.1;7.5.1 Analog LED Technology;380
10.5.2;7.5.2 LED Drivers;382
10.5.3;7.5.3 Light Management Units;383
10.5.3.1;7.5.3.1 Switch Pin Protection;386
10.5.3.2;7.5.3.2 Feedback Pin Protection;386
10.5.3.3;7.5.3.3 LED Driver Protection;387
10.5.3.4;7.5.3.4 Gate Cl388
10.5.3.5;7.5.3.5 RGB Driver;388
10.5.3.6;7.5.3.6 Control Pins;389
10.5.3.7;7.5.3.7 Current Sink Protection;390
10.6;7.6 A Few More Case Studies;390
10.6.1;7.6.1 Power Array--ESD Clamp Interaction;390
10.6.2;7.6.2 Nepi--Nepi Transient Latch-Up Scenario;393
10.6.3;7.6.3 CDM Case of the High-Voltage Pin Protection;396
10.7;7.7 Summary;399
10.8;DECIMMTM Simulation Examples for Chapter 7;403
10.8.1;Example 7.1 Output Stage of Buck DC--DC Voltage Regulator;403
10.8.2;Example 7.2 5--V Boost DC--DC Converter and Transient Latch-Up;404
10.8.3;Example 7.3 High-Voltage Boost Output Stage;405
10.8.4;Example 7.4 100 600 V Boost Output Stage with Vertical DMOS and IGBT;406
10.8.5;Example 7.5 Power Array with Gate Clamp Example;406
10.8.6;Example 7.6 Serial Data Line Pin Case;407
11;8 System-Level and Discrete Components ESD;410
11.1;8.1 System-Level Specifications and Standards;411
11.1.1;8.1.1 Meaning of ESD Robust System;411
11.1.1.1;8.1.1.1 CE Mark;412
11.1.1.2;8.1.1.2 Basic EMC Standards;412
11.1.1.3;8.1.1.3 Automotive Industry Standards;412
11.1.1.4;8.1.1.4 IC and System-Level Comparison;413
11.1.2;8.1.2 System-Level ESD Pulse and Model;415
11.1.2.1;8.1.2.1 System-Level ESD Test for ICs;415
11.1.2.2;8.1.2.2 IEC ESD Pulse Waveforms;415
11.1.2.3;8.1.2.3 System-Level Test Setup;418
11.1.2.4;8.1.2.4 Cable Discharge Event (CDE);419
11.1.3;8.1.3 Transient Latch-up During a System-Level Event;420
11.1.4;8.1.4 System-Level Protection Components;423
11.2;8.2 On-Wafer Human Metal Model Measurements;424
11.2.1;8.2.1 On-Wafer HMM Tester and Equivalent Circuit of the Pulse;425
11.2.1.1;8.2.1.1 Equivalent Circuit for HMM Simulation;426
11.2.2;8.2.2 HMM-HBM Component Correlation;427
11.2.2.1;8.2.2.1 Diodes Under HMM Stress;429
11.2.2.2;8.2.2.2 LVTSCR;429
11.2.2.3;8.2.2.3 High-Voltage ESD Clamps;430
11.3;8.3 On-Chip Design for System-Level Pins;431
11.3.1;8.3.1 Examples of Circuits with System-Level Protection;431
11.3.1.1;8.3.1.1 On-Chip and Suppressor ESD Device Interaction;436
11.4;8.4 Hot Swap and Hot Plug-in;437
11.4.1;8.4.1 The Concept of Two-Stage SCR ESD Devices;437
11.5;8.5 System-on-Package (SOP) Protection;443
11.6;8.6 ESD Robustness of Discrete Components;444
11.6.1;8.6.1 Discrete Components in High Reliability Systems;444
11.6.2;8.6.2 ESD Requirement for Discrete Components;444
11.6.2.1;8.6.2.1 ESD Effects on Power Transistors;445
11.6.2.2;8.6.2.2 Statistical Approach for ESD and Reliability Parameters Verification;446
11.6.3;8.6.3 Preliminary Numerical Analysis for Devices with Defects and the Two-Transistor Model;447
11.6.4;8.6.4 Experimental Evaluation of Discrete Components Discrete Components Robustness;451
11.6.4.1;8.6.4.1 TLP Stress;452
11.6.4.2;8.6.4.2 ISO System-Level Pulse Test;453
11.6.4.3;8.6.4.3 Collector--Emitter ISO Test;454
11.6.4.4;8.6.4.4 Gate--Collector ISO Tests;456
11.7;8.7 Summary;457
11.8;DECIMM TM Simulation Examples for Chapter 8;458
11.8.1;Example 8.1 System HMM Pulse Simulation;458
11.8.2;Example 8.2 HMM Simulation with PCB Components and TVS;458
11.8.3;Example 8.3 Power Switch;458
12;References;462
13;Index;470