Siewiorek / Swarz Reliable Computer Systems

Design and Evaluatuion
2. Auflage 2014
ISBN: 978-1-4832-9743-9
Verlag: Elsevier Science & Techn.
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 908 Seiten, Web PDF

Enhance your hardware/software reliability Enhancement of system reliability has been a major concern of computer users and designers ¦ and this major revision of the 1982 classic meets users' continuing need for practical information on this pressing topic. Included are case studies of reliable systems from manufacturers such as Tandem, Stratus, IBM, and Digital, as well as coverage of special systems such as the Galileo Orbiter fault protection system and AT&T telephone switching processors.

Autoren/Hrsg.

Siewiorek, Daniel

Swarz, Robert

Inhaltsverzeichnis

1;Front Cover;1
2;Reliable Computer Systems: Design and Evaluation;4
3;Copyright Page;5
4;Table of Contents;8
5;Dedication;6
6;Preface;16
7;PART I: THE THEORY OF RELIABLE SYSTEM DESIGN;22
7.1;CHAPTER 1. FUNDAMENTAL CONCEPTS;24
7.1.1;Physical Levels in a Digital System;26
7.1.2;Temporal Stages of a Digital System;27
7.1.3;Cost of a Digital System;39
7.1.4;Summary;42
7.1.5;References;42
7.2;CHAPTER 2 . FAULTS AND THEIR MANIFESTATIONS;43
7.2.1;System Errors;45
7.2.2;Fault Manifestations;52
7.2.3;Fault Distributions;70
7.2.4;Distribution Models for Permanent Faults: The MIL-HDBK-217 Model;78
7.2.5;Distribution Models for Intermittent and Transient Faults;86
7.2.6;Software Fault Models;94
7.2.7;Summary;97
7.2.8;References;97
7.2.9;Problems;98
7.3;CHAPTER
3. RELIABILITY TECHNIQUES;100
7.3.1;System-Failure Response Stages;101
7.3.2;Hardware Fault-Avoidance Techniques;105
7.3.3;Hardware Fault-Detection Techniques;117
7.3.4;Hardware Masking Redundancy Techniques;159
7.3.5;Hardware Dynamic Redundancy Techniques;190
7.3.6;Software Reliability Techniques;222
7.3.7;Summary;240
7.3.8;References;240
7.3.9;Problems;242
7.4;CHAPTER
4. MAINTAINABILITY AND TESTING TECHNIQUES;249
7.4.1;Specification-Based Diagnosis;250
7.4.2;Symptom-Based Diagnosis;281
7.4.3;Summary;289
7.4.4;References;289
7.4.5;Problems;290
7.5;CHAPTER
5. EVALUATION CRITERIA;292
7.5.1;Introduction;292
7.5.2;Survey of Evaluation Criteria: Hardware;293
7.5.3;Survey of Evaluation Criteria: Software;300
7.5.4;Reliability Modeling Techniques: Combinatorial Models;306
7.5.5;Examples of Combinatorial Modeling;315
7.5.6;Reliability and Availability Modeling Techniques: Markov Models;326
7.5.7;Examples of Markov Modeling;355
7.5.8;Availability Modeling Techniques;363
7.5.9;Software Assistance for Modeling Techniques;370
7.5.10;Applications of Modeling Techniques to Systems Designs;377
7.5.11;Summary;412
7.5.12;References;412
7.5.13;Problems;413
7.6;CHAPTER
6. FINANCIAL CONSIDERATIONS;423
7.6.1;Fundamental Concepts;423
7.6.2;Cost Models;429
7.6.3;Summary;440
7.6.4;References;440
7.6.5;Problems;441
8;PART II: THE PRACTICE OF RELIABLE SYSTEM DESIGN;444
8.1;Fundamental Concep;445
8.2;General-Purpose Computing;445
8.3;High-Availability Systems;445
8.4;Long-Life Systems;446
8.5;Critical Computations;446
8.6;CHAPTER
7. GENERAL-PURPOSE COMPUTING;448
8.6.1;Introduction;448
8.6.2;Generic Computer;448
8.6.3;DEC;451
8.6.4;IBM;452
8.6.5;The DEC Case: RAMP in the VAX Family;454
8.6.6;The VAX Architecture;454
8.6.7;First-Generation VAX Implementations;460
8.6.8;Second-Generation VAX Implementations;476
8.6.9;References;505
8.6.10;The IBM Case Part I: Reliability, Availability, and Serviceability in IBM 308X and IBM 3090 Processor Complexes;506
8.6.11;Technology;506
8.6.12;Manufacturing;507
8.6.13;Overview of the 3090 Processor Complex;514
8.6.14;References;528
8.6.15;The IBM Case Part II: Recovery Through Programming: MVS Recovery Management;529
8.6.16;Introduction;529
8.6.17;RAS Objectives;530
8.6.18;Overview of Recovery Management;530
8.6.19;MVS/XA Hardware Error Recovery;532
8.6.20;MVS/XA Serviceability Facilities;541
8.6.21;Availability;543
8.6.22;Summary;544
8.6.23;Bibliography;544
8.6.24;Reference;544
8.7;CHAPTER
8. HIGH-AVAILABILITY SYSTEMS;545
8.7.1;Introduction;545
8.7.2;AT&T Switching Systems;545
8.7.3;Tandem Computers, Inc;549
8.7.4;Stratus Computers, Inc;552
8.7.5;References;554
8.7.6;The AT&T Case Part I: Fault-Tolerant Design of AT&T Telephone Switching System Processors;554
8.7.7;Introduction;554
8.7.8;Allocation and Causes of System Downtime;555
8.7.9;Duplex Architecture;556
8.7.10;Fault Simulation Techniques;559
8.7.11;First-Generation ESS Processors;561
8.7.12;Second-Generation Processors;565
8.7.13;Third-Generation 3B20D Processor;572
8.7.14;Summary;593
8.7.15;References;594
8.7.16;The AT&T Case Part II: Large-Scale Real-Time Program Retrofit Methodology in AT&T 5ESS® Switch;595
8.7.17;5ESS Switch Architecture Overview;595
8.7.18;Software Replacement;597
8.7.19;Summary;606
8.7.20;References;607
8.7.21;The Tandem Case: Fault Tolerance in Tandem Computer Systems;607
8.7.22;Hardware;609
8.7.23;Processor Module Implementation Details;618
8.7.24;Integrity S2;639
8.7.25;Maintenance Facilities and Practices;643
8.7.26;Software;646
8.7.27;Operations;668
8.7.28;Summary and Conclusions;668
8.7.29;References;669
8.7.30;The Stratus Case: The Stratus Architecture;669
8.7.31;Stratus Solutions to Downtime;671
8.7.32;Issues of Fault Tolerance;673
8.7.33;System Architecture Overview;674
8.7.34;Recovery Scenarios;685
8.7.35;Architecture Tradeoffs;686
8.7.36;Stratus Software;687
8.7.37;Service Strategies;690
8.7.38;Summary;691
8.8;CHAPTER
9. LONG-LIFE SYSTEMS;692
8.8.1;Introduction;692
8.8.2;Generic Spacecraft;692
8.8.3;Deep-Space Planetary Probes;697
8.8.4;Other Noteworthy Spacecraft Designs;700
8.8.5;References;700
8.8.6;The Galileo Case: Galileo Orbiter Fault Protection System;700
8.8.7;The Galileo Spacecraft;701
8.8.8;Attitude and Articulation Control Subsystem;701
8.8.9;Command and Data Subsystem;704
8.8.10;AACS/CDS Interactions;708
8.8.11;Sequences and Fault Protection;709
8.8.12;Fault-Protection Design Problems and Their Resolution;710
8.8.13;Summary;711
8.8.14;References;711
8.9;CHAPTER
10. CRITICAL COMPUTATIONS;712
8.9.1;Introduction;712
8.9.2;C.vmp;712
8.9.3;SIFT;714
8.9.4;The C.vmp Case: A Voted Multiprocessor;715
8.9.5;System Architecture;715
8.9.6;Issues of Processor Synchronization;720
8.9.7;Performance Measurements;723
8.9.8;Operational Experiences;728
8.9.9;References;730
8.9.10;The SIFT Case: Design and Analysis of a Fault-Tolerant Computer for Aircraft Control;731
8.9.11;Motivation and Background;731
8.9.12;SIFT Concept of Fault Tolerance;732
8.9.13;The SIFT Hardware;740
8.9.14;The Software System;744
8.9.15;The Proof of Correctness;749
8.9.16;Summary;754
8.9.17;Appendix: Sample Special Specification;754
8.9.18;References;756
9;PART III: A DESIGN METHODOLOGY AND EXAMPLE OF DEPENDABLE SYSTEM DESIGN;758
9.1;CHAPTER
11. A DESIGN METHODOLOGY;760
9.1.1;Introduction;760
9.1.2;A Design Methodology for Dependable System Design;760
9.1.3;The VAXft 310 Case: A Fault-Tolerant System by Digital Equipment Corporation;766
9.1.4;Defining Design Goals and Requirements for the VAXft 310;767
9.1.5;VAXft 310 Overview;768
9.1.6;Details of VAXft 310 Operation;777
9.1.7;Summary;787
10;APPENDIXES;790
10.1;APPENDIX A;792
10.1.1;Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review;792
10.1.2;Introduction;792
10.1.3;Binary Linear Block Codes;794
10.1.4;SEC-DEC Codes;796
10.1.5;SEC-DED-SBD Codes;799
10.1.6;SBC-DBD Codes;800
10.1.7;DEC-TED Codes;802
10.1.8;Extended Error Correction;805
10.1.9;Conclusions;807
10.1.10;References;807
10.2;APPENDIX B;808
10.2.1;Arithmetic Error Codes: Cost and Effectiveness Studies for Application in Digital System Design;808
10.2.2;Methodology of Code Evaluation;808
10.2.3;Fault Effects in Binary Arithmetic Processors;811
10.2.4;Low-Cost Radix-2 Arithmetic Codes;815
10.2.5;Multiple Arithmetic Error Codes;820
10.2.6;References;823
10.3;APPENDIX C;824
10.3.1;Design for Testability—A Survey;824
10.3.2;Introduction;824
10.3.3;Design for Testability;828
10.3.4;Ad-Hoc Design for Testability;829
10.3.5;Structured Design for Testability;834
10.3.6;Self-Testing and Built-in Tests;842
10.3.7;Conclusion;849
10.3.8;References;850
10.4;APPENDIX D;852
10.4.1;Summary of MIL-HDBK-217E Reliability Model;852
10.4.2;Failure Rate Model and Factors;852
10.4.3;Reference;854
10.5;APPENDIX E;856
10.5.1;Algebraic Solutions to Markov Models;856
10.5.2;Solution of MTTF Models;858
10.5.3;Complete Solution for Three- and Four-State Models;859
10.5.4;Solutions to Commonly Encountered Markov Models;860
10.5.5;References;860
11;GLOSSARY;862
12;REFERENCES;866
13;CREDITS;906
14;TRADEMARKS;911
15;INDEX;912