Silvano / Lajolo / Palermo Low Power Networks-on-Chip

1. Auflage 2010
ISBN: 978-1-4419-6911-8
Verlag: Springer
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 287 Seiten

In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.

Autoren/Hrsg.

Silvano, Cristina

Lajolo, Marcello

Palermo, Gianluca

Inhaltsverzeichnis

1;Preface;8
2;About the Editors;14
3;Contents;16
4;Contributors;18
5;Part I Low-Level Design Techniques;22
5.1;Chapter 1 Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections;23
5.1.1;1.1 Network on-Chip: Past, Present, and the Future;23
5.1.1.1;1.1.1 State of the Art in NoCs;24
5.1.1.1.1;1.1.1.1 Buses;24
5.1.1.1.2;1.1.1.2 Rings;24
5.1.1.1.3;1.1.1.3 Meshes;25
5.1.1.2;1.1.2 Issues and Challenges for the Future;25
5.1.1.2.1;1.1.2.1 Power and Energy;25
5.1.1.2.2;1.1.2.2 Heterogeneity;26
5.1.2;1.2 Proposed Hybrid Packet/Circuit Switched NoC;27
5.1.2.1;1.2.1 Circuit-Switched Data with Packet-Switched Arbitration NoC;27
5.1.2.2;1.2.2 Circuit Innovations for Circuit/Packet Switched Network Arbitration;30
5.1.2.3;1.2.3 Data Transmission Circuit Innovations;33
5.1.3;1.3 NoC Measurements and Tradeoffs in 45nm CMOS;35
5.1.4;1.4 Conclusion;39
5.1.5;References;39
5.2;Chapter 2 Run-Time Power-Gating Techniques for Low-Power On-Chip Networks;41
5.2.1;2.1 Introduction;41
5.2.2;2.2 On-Chip Virtual-Channel Router;42
5.2.2.1;2.2.1 Target Router Architecture;42
5.2.2.2;2.2.2 Power Analysis of the Target Router Architecture;44
5.2.3;2.3 Previous Work on Low-Power Techniques;45
5.2.3.1;2.3.1 Voltage and Frequency Scaling Techniques;45
5.2.3.2;2.3.2 Power Gating Techniques;46
5.2.3.2.1;2.3.2.1 Coarse-Grained Power-Gating Techniques;46
5.2.3.2.2;2.3.2.2 Fine-Grained Power Gating Techniques;46
5.2.3.2.3;2.3.2.3 Power Gating for Interconnection Networks;47
5.2.4;2.4 Fine-Grained Power Gating Router;48
5.2.4.1;2.4.1 Power Domain Partitioning;48
5.2.4.2;2.4.2 Power Domain Implementation;49
5.2.4.3;2.4.3 Wakeup Latency Estimation;50
5.2.5;2.5 Wakeup Control Methods;51
5.2.5.1;2.5.1 Wakeup Latency Impact;51
5.2.5.2;2.5.2 Look-Ahead Method;52
5.2.5.3;2.5.3 Look-Ahead with Ever-On Method;54
5.2.5.4;2.5.4 Look-Ahead with Active Buffer Window Method;54
5.2.6;2.6 Experimental Evaluations;55
5.2.6.1;2.6.1 Simulation Environment;55
5.2.6.2;2.6.2 Performance Impact;57
5.2.6.3;2.6.3 Leakage Power Reduction;59
5.2.7;2.7 Summary;60
5.2.8;References;62
5.3;Chapter 3 Adaptive Voltage Control for Energy-Efficient NoC Links;64
5.3.1;3.1 Introduction;64
5.3.2;3.2 Methods for Energy-Efficient On-Chip Links;65
5.3.2.1;3.2.1 Metrics for Energy Efficiency;65
5.3.2.2;3.2.2 Datalink Layer Techniques;66
5.3.2.2.1;3.2.2.1 Bus Invert and Extended Bus Invert Coding;66
5.3.2.2.2;3.2.2.2 Frequent Value Coding;66
5.3.2.2.3;3.2.2.3 Crosstalk Avoidance Coding;67
5.3.2.2.4;3.2.2.4 Asymptotic Zero-Transition Coding;67
5.3.2.3;3.2.3 Physical Layer Techniques;68
5.3.2.3.1;3.2.3.1 Low-Swing Signaling;68
5.3.2.3.2;3.2.3.2 Differential Signaling;69
5.3.2.3.3;3.2.3.3 Repeater Insertion;69
5.3.2.3.4;3.2.3.4 Dual-Voltage Buffers;70
5.3.2.3.5;3.2.3.5 Pulsed Transmission;70
5.3.2.3.6;3.2.3.6 Current Mode Signaling;71
5.3.2.3.7;3.2.3.7 Globally Asynchronous Locally Synchronous (GALS) Signaling;71
5.3.2.3.8;3.2.3.8 Quasi-Resonant Interconnect;71
5.3.2.3.9;3.2.3.9 Adaptive Link Voltage Scaling;72
5.3.2.4;3.2.4 Other Methods;72
5.3.2.4.1;3.2.4.1 Integrating Double Sampling with Adaptive Voltage Scaling;72
5.3.2.4.2;3.2.4.2 Combining Error Control Coding with Adaptive Voltage Scaling;72
5.3.3;3.3 Lookahead-Based Transition-Aware Link Voltage Control;73
5.3.3.1;3.3.1 Lookahead Transmitter Design;74
5.3.3.2;3.3.2 HI/LO Voltage Selection;77
5.3.3.3;3.3.3 Performance Evaluation;78
5.3.3.3.1;3.3.3.1 Comparison with Traditional Two-Inverter Driver;79
5.3.3.3.2;3.3.3.2 Comparison with Adaptive Voltage Driver;81
5.3.3.3.3;3.3.3.3 Comparison with Prior Dual-Voltage Switching Method;83
5.3.3.4;3.3.4 Limitations;84
5.3.4;References;86
5.4;Chapter 4 Asynchronous Communications for NoCs;89
5.4.1;4.1 Introduction;90
5.4.1.1;4.1.1 Variability;91
5.4.1.2;4.1.2 Power Consumption;92
5.4.1.3;4.1.3 Chapter Structure;93
5.4.2;4.2 History of Asynchronous Communications Before the NoC Era;94
5.4.3;4.3 Token-Based View of Communication;95
5.4.4;4.4 Basics of Asynchronous Signalling;97
5.4.4.1;4.4.1 Signalling Techniques;97
5.4.4.2;4.4.2 Handshake Protocols;98
5.4.4.3;4.4.3 Channel Types;99
5.4.5;4.5 Delay-Insensitive Data Communication;100
5.4.5.1;4.5.1 Dual-rail;100
5.4.5.2;4.5.2 1-of-N and M-of-N;101
5.4.5.3;4.5.3 Single Transition Codes;104
5.4.6;4.6 Delay-Sensitive Communication;105
5.4.6.1;4.6.1 Bundled-Data Encoding;105
5.4.6.2;4.6.2 Single-Track Signalling;106
5.4.6.3;4.6.3 Pulse-Based Signalling;106
5.4.7;4.7 SEU Resilient Codes;107
5.4.7.1;4.7.1 Phase Encoding;107
5.4.7.2;4.7.2 Data-Reference Codes;108
5.4.7.3;4.7.3 Summary on Codes;109
5.4.8;4.8 Pipelining;110
5.4.8.1;4.8.1 Paired Handshake;111
5.4.8.2;4.8.2 Serial vs. Parallel Links;112
5.4.9;4.9 Networks-on-Chip;113
5.4.10;4.10 Synchronizers;115
5.4.10.1;4.10.1 Design of a Simple Synchronizer;116
5.4.11;4.11 Routers;118
5.4.11.1;4.11.1 Arbiters;119
5.4.12;4.12 CAD Issues;120
5.4.12.1;4.12.1 Logic Synthesis;120
5.4.12.2;4.12.2 Syntax-Driven Design;121
5.4.12.3;4.12.3 Example of Synthesis Using Petrify;121
5.4.13;4.13 Conclusions;124
5.4.14;References;124
6;Part II System-Level Design Techniques;128
6.1;Chapter 5 Application-Specific Routing Algorithms for Low Power Network on Chip Design;129
6.1.1;5.1 Introduction;129
6.1.2;5.2 Background on Routing Algorithms and Power Dissipation;131
6.1.2.1;5.2.1 Classification of Routing Algorithms;131
6.1.2.2;5.2.2 Wormhole Switching and Deadlock;132
6.1.2.3;5.2.3 Basic Components of a Routing Algorithm;133
6.1.2.3.1;5.2.3.1 Routing Function;133
6.1.2.3.2;5.2.3.2 Selection Function;134
6.1.2.4;5.2.4 Routing Logic and Hardware Implications;135
6.1.2.5;5.2.5 Region Concept in NoC;136
6.1.2.6;5.2.6 Network Energy and Routing Algorithms;137
6.1.2.7;5.2.7 Common Performance Metrics;138
6.1.3;5.3 Terminology and Definitions;138
6.1.3.1;5.3.1 Basic Definitions;138
6.1.3.2;5.3.2 Channel Dependency Graph and Deadlock Freedom;139
6.1.3.3;5.3.3 Application-Specific Channel Dependency Graph;140
6.1.3.4;5.3.4 Routing Adaptivity;141
6.1.4;5.4 APSRA Design Methodology;141
6.1.4.1;5.4.1 APSRA by Example;141
6.1.4.2;5.4.2 Main Algorithm;144
6.1.4.3;5.4.3 Cutting Edge with Minimum Loss of Adaptivity;144
6.1.4.4;5.4.4 Routing Tables;147
6.1.4.4.1;5.4.4.1 Routing Table Compression;147
6.1.5;5.5 Performance Evaluation of APSRA;149
6.1.5.1;5.5.1 Traffic Scenarios;149
6.1.5.2;5.5.2 Adaptivity Analysis;151
6.1.5.3;5.5.3 Simulation Based Evaluation;152
6.1.5.3.1;5.5.3.1 Homogeneous 2D Mesh NoC;153
6.1.5.3.2;5.5.3.2 NonHomogeneous 2D Mesh NoC with Regions;155
6.1.6;5.6 Cost, Power Dissipation and Energy Consumption Analysis;159
6.1.6.1;5.6.1 Generic Router Architecture;159
6.1.6.2;5.6.2 Area and Power Dissipation;160
6.1.6.3;5.6.3 Energy Consumption;162
6.1.7;5.7 Conclusions;163
6.1.8;References;164
6.2;Chapter 6 Adaptive Data Compression for Low-Power On-Chip Networks;167
6.2.1;6.1 Introduction;167
6.2.2;6.2 Related Work;169
6.2.3;6.3 Data Compression In On-Chip Networks;170
6.2.3.1;6.3.1 On-Chip Network Architecture;170
6.2.3.2;6.3.2 Compression Support;172
6.2.3.3;6.3.3 Table Organization;174
6.2.4;6.4 Optimizing Compression;174
6.2.4.1;6.4.1 Shared Table Structure;174
6.2.4.2;6.4.2 Shared Table Consistency Management;176
6.2.4.3;6.4.3 Increasing Compression Effectiveness;176
6.2.5;6.5 Methodology;178
6.2.6;6.6 Experimental Results;179
6.2.6.1;6.6.1 Compressibility and Value Pattern;180
6.2.6.2;6.6.2 Effect on Power Consumption;182
6.2.6.3;6.6.3 Effect on Packet Latency;184
6.2.6.4;6.6.4 Compression Table Area Analysis;186
6.2.6.5;6.6.5 Comparison with Wide/Long-Channel Networks;187
6.2.7;6.7 Conclusion;188
6.2.8;References;189
6.3;Chapter 7 Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: A Case Study;191
6.3.1;7.1 Introduction;191
6.3.2;7.2 Related Work;193
6.3.3;7.3 The Target Application;194
6.3.4;7.4 NoC Design and Optimization;197
6.3.4.1;7.4.1 Cost-Optimized Mapping;198
6.3.4.2;7.4.2 Setting Link Capacities;200
6.3.5;7.5 Experimental Results;203
6.3.5.1;7.5.1 Target Router Architecture;204
6.3.5.2;7.5.2 Synthesis Results;206
6.3.6;7.6 Summary and Conclusions;209
6.3.7;References;210
7;Part III Future and Emerging Technologies;212
7.1;Chapter 8 Design and Analysis of NoCs for Low-Power 2D and 3D SoCs ;213
7.1.1;8.1 Introduction;213
7.1.2;8.2 Architecture with Voltage Island Support;216
7.1.2.1;8.2.1 2D SoC Architecture;216
7.1.3;8.3 3D SoC Architecture;218
7.1.4;8.4 Design Approach;218
7.1.4.1;8.4.1 Synthesis Problem Formulation;219
7.1.5;8.5 Synthesis Algorithm for 2D ICs with VI Shutdown;220
7.1.6;8.6 Extension for 3D ICs;224
7.1.7;8.7 Experimental Results;225
7.1.7.1;8.7.1 Design of 2D ICs;225
7.1.7.2;8.7.2 Baseline Comparison of 2D and 3D ICs;230
7.1.7.3;8.7.3 Comparison for Different Number of Voltage and Frequency Islands;230
7.1.7.4;8.7.4 Analysis of Results;233
7.1.8;8.8 Conclusions;234
7.1.9;References;234
7.2;Chapter 9 CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study;237
7.2.1;9.1 Introduction;238
7.2.2;9.2 CMOS Nanophotonic Technologies;240
7.2.2.1;9.2.1 Overview;241
7.2.2.2;9.2.2 Sources;242
7.2.2.3;9.2.3 Waveguides, Splitters, Couplers and Connectors;243
7.2.2.4;9.2.4 Detectors;244
7.2.2.5;9.2.5 Technology for Intra- and Inter-Chip Communication;244
7.2.3;9.3 Nanophotonic Network Principles;245
7.2.3.1;9.3.1 Electrical Interconnects;246
7.2.3.2;9.3.2 Optical Interconnect;247
7.2.3.3;9.3.3 Photonic Network Fundamentals;249
7.2.3.4;9.3.4 Optical Arbitration;250
7.2.3.5;9.3.5 Optical Barriers;252
7.2.4;9.4 Corona: A Nanophotonic Case Study;253
7.2.4.1;9.4.1 Corona Architecture;254
7.2.4.2;9.4.2 Experimental Setup;261
7.2.4.3;9.4.3 Performance Evaluation;263
7.2.5;9.5 Summary;265
7.2.6;References;266
7.3;Chapter 10 RF-Interconnect for Future Network-On-Chip;269
7.3.1;10.1 Introduction;269
7.3.2;10.2 Interconnect Problem in Future Information Processor;270
7.3.3;10.3 How Can RF Help?;272
7.3.4;10.4 Expected Performance of RF-I with Scaling;275
7.3.5;10.5 Implementation Examples;275
7.3.5.1;10.5.1 On-Chip Multi-Carrier Generation;275
7.3.5.2;10.5.2 On-Chip RF-Interconnect;277
7.3.5.3;10.5.3 3D IC RF-Interconnect;284
7.3.6;10.6 Impact of RF-I in Future SoC/NoC Architecture;286
7.3.7;10.7 Future RF-I Research Direction ;287
7.3.8;References;293
8;Index;295