Sites / Witek Alpha AXP Architecture Reference Manual

2. Auflage 2014
ISBN: 978-1-4831-8403-6
Verlag: Elsevier Science & Techn.
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 858 Seiten, Web PDF

Alpha AXP Architecture Reference Manual, Second Edition describes the required behavior of all Alpha implementations, as seen by the machine-language programmer. This book discusses Alpha single-board computers, which have been introduced to cover the high-end embedded controller market. Organized into five parts, this edition begins with an overview of the instruction-set architecture. This text then describes the supporting PALcode routines for three operating systems. Other parts consider a particular console implementation that is specific to platforms that support the OpenVMS AXP or DEC OSF/1 operating systems. This book discusses as well the specific operating system PALcode architecture. The final part provides a discussion of console issues for Windows NT with its PALcode description. This book is a valuable resource for machine-language programmers.

Autoren/Hrsg.

Sites, Richard L.

Witek, Richard T.

Inhaltsverzeichnis

1;Front Cover;1
2;Alpha Axp Architecture Reference Manual;4
3;Copyright Page;5
4;Table of Contents;6
5;FOREWORD;8
6;Preface to the First Edition;12
7;Preface to the Second Edition;16
8;Part 1: Common Architecture (I);18
8.1;Chapter 1. Introduction (I);28
8.1.1;1.1 The Alpha AXP Approach to RISC Architecture;28
8.1.2;1.2 Data Format Overview;30
8.1.3;1.3 Instruction Format Overview;31
8.1.4;1.4 Instruction Overview;32
8.1.5;1.5 Instruction Set Characteristics;33
8.1.6;1.6 Terminology and Conventions;34
8.2;Chapter 2. Basic Architecture (I);38
8.2.1;2.1 Addressing;38
8.2.2;2.2 Data Types;38
8.2.3;2.3 Big-endian Addressing Support;51
8.3;Chapter 3. Instruction Formats (I);54
8.3.1;3.1 Alpha AXP Registers;54
8.3.2;3.2 Notation;56
8.3.3;3.3 Instruction Formats;62
8.4;Chapter 4. Instruction Descriptions (I);68
8.4.1;4.1 Instruction Set Overview;68
8.4.2;4.2 Memory Integer Load/Store Instructions;71
8.4.3;4.3 Control Instructions;83
8.4.4;4.4 Integer Arithmetic Instructions;90
8.4.5;4.5 Logical and Shift Instructions;104
8.4.6;4.6 Byte-Manipulation Instructions;110
8.4.7;4.7 Floating-Point Instructions;124
8.4.8;4.8 Memory Format Floating-Point Instructions;145
8.4.9;4.9 Branch Format Floating-Point Instructions;154
8.4.10;4.10 Floating-Point Operate Format Instructions;157
8.4.11;4.11 Miscellaneous Instructions;186
8.4.12;4.12 VAX Compatibility Instructions;195
8.5;Chapter 5. System Architecture and Programming Implications;198
8.5.1;5.1 Introduction;198
8.5.2;5.2 Physical Address Space Characteristics;198
8.5.3;5.3 Translation Buffers and Virtual Caches;201
8.5.4;5.4 Caches and Write Buffers;201
8.5.5;5.5 Data Sharing;202
8.5.6;5.6 Read/Write Ordering;206
8.5.7;5.7 Arithmetic Traps;223
8.6;Chapter 6. Common PALcode Architecture (I);226
8.6.1;6.1 PALcode;226
8.6.2;6.2 PALcode Instructions and Functions;226
8.6.3;6.3 PALcode Environment;227
8.6.4;6.4 Special Functions Required for PALcode;227
8.6.5;6.5 PALcode Effects on System Code;228
8.6.6;6.6 PALcode Replacement;228
8.6.7;6.7 Required PALcode Instructions;229
8.7;Chapter 7. Console Subsystem Overview (I);236
8.8;Chapter 8. Input/Output Overview (I);238
8.9;Specific Operating System PALcode Architecture (II);240
9;Part 2: OpenVMS AXP Software (ll–A);242
9.1;Chapter 1. Introduction to OpenVMS AXP (II–A);252
9.1.1;1.1 Register Usage;252
9.2;Chapter 2. OpenVMS AXP PALcode Instruction Descriptions (ll–A);254
9.2.1;2.1 Unprivileged General OpenVMS AXP PALcode Instructions;256
9.2.2;2.2 OpenVMS AXP Queue Data Types;274
9.2.3;2.3 Unprivileged OpenVMS AXP Queue PALcode Instructions;283
9.2.4;2.4 Unprivileged VAX Compatibility PALcode Instructions;329
9.2.5;2.5 Unprivileged PALcode Thread Instructions;334
9.2.6;2.6 Privileged PALcode Instructions;337
9.3;Chapter 3. OpenVMS AXP Memory Management (II–A);350
9.3.1;3.1 Introduction;350
9.3.2;3.2 Virtual Address Space;350
9.3.3;3.3 Physical Address Space;352
9.3.4;3.4 Memory Management Control;352
9.3.5;3.5 Page Table Entries;352
9.3.6;3.6 Memory Protection;356
9.3.7;3.7 Address Translation;357
9.3.8;3.8 Translation Buffer;360
9.3.9;3.9 Address Space Numbers;361
9.3.10;3.10 Memory Management Faults;361
9.4;Chapter 4. OpenVMS AXP Process Structure (II–A);364
9.4.1;4.1 Process Definition;364
9.4.2;4.2 Hardware Privileged Process Context;365
9.4.3;4.3 Asynchronous System Traps (AST);367
9.4.4;4.4 Process Context Switching;367
9.5;Chapter 5. OpenVMS AXP Internal Processor Registers (ll–A);370
9.5.1;5.1 Internal Processor Registers;370
9.5.2;5.1 Internal Processor Registers;370
9.5.3;5.2 Stack Pointer Internal Processor Registers;370
9.5.4;5.3 IPR Summary;371
9.6;Chapter 6. OpenVMS AXP Exceptions, Interrupts, and Machine Checks (ll–A);402
9.6.1;6.1 Introduction;402
9.6.2;6.2 Processor State and Exception/Interrupt/Machine Check Stack Frame;407
9.6.3;6.3 Exceptions;410
9.6.4;6.4 Interrupts;420
9.6.5;6.5 Machine Checks;425
9.6.6;6.6 System Control Block;428
9.6.7;6.7 PALcode Support;434
10;Part 3: DEC OSF/1 Software (II–B);442
10.1;Chapter 1. Introduction to DEC OSF/1 (II–B);448
10.1.1;1.1 Programming Model;449
10.2;Chapter 2. DEC OSF/1 PALcode Instruction Descriptions (II–B);454
10.2.1;2.1 Unprivileged PALcode Instructions;454
10.2.2;2.2 Privileged DEC OSF/1 PALcode Instructions;461
10.3;Chapter 3. DEC OSF/1 Memory Management (II–B);488
10.3.1;3.1 Virtual Address Spaces;488
10.3.2;3.2 Physical Address Space;490
10.3.3;3.3 Memory Management Control;490
10.3.4;3.4 Page Table Entries;490
10.3.5;3.5 Memory Protection;493
10.3.6;3.6 Address Translation for Seg0 and Seg1;494
10.3.7;3.7 Translation Buffer;495
10.3.8;3.8 Address Space Numbers;496
10.3.9;3.9 Memory-Management Faults;497
10.4;Chapter 4. DEC OSF/1 Process Structure (II–B);498
10.4.1;4.1 Process Definition;498
10.4.2;4.2 Process Control Block (PCB);498
10.5;Chapter 5. DEC OSF/1 Exceptions and Interrupts (II–B);502
10.5.1;5.1 Introduction;502
10.5.2;5.2 Processor Status;503
10.5.3;5.3 Stack Frames;504
10.5.4;5.4 System Entry Addresses;505
10.5.5;5.5 PALcode Support;510
11;Part 4: Windows NT AXP Software (ll–C);512
11.1;Chapter 1. Introduction to Windows NT AXP Software (II–C);518
11.1.1;1.1 Overview of System Components;519
11.1.2;1.2 Calling Standard Register Usage;520
11.1.3;1.3 Code Flow Conventions;521
11.2;Chapter 2. Processor, Process, and Thread Structures and Registers (II–C);522
11.2.1;2.1 Processor Status;522
11.2.2;2.2 Internal Processor Register Summary;523
11.2.3;2.3 Internal Processor Registers;524
11.2.4;2.4 Processor Data Areas;527
11.2.5;2.5 Caches and Cache Coherency;528
11.2.6;2.6 Stacks;528
11.2.7;2.7 Processes and Threads;529
11.3;Chapter 3. Memory Management (II–C);532
11.3.1;3.1 Virtual Address Space;532
11.3.2;3.2 I/O Space Address Extension;532
11.3.3;3.3 Canonical Virtual Address Format;533
11.3.4;3.4 Page Table Entries;533
11.3.5;3.5 Translation Buffer Management;536
11.3.6;3.6 Implications of Recursive TB Mapping;537
11.4;Chapter 4. Exceptions, Interrupts, and Machine Checks (ll–C);540
11.4.1;4.1 Exceptions;540
11.4.2;4.2 Interrupts;551
11.4.3;4.3 Machine Checks;556
11.5;Chapter 5. Windows NT AXP PALcode Instruction Descriptions (ll–C);560
11.5.1;5.1 Privileged PALcode Instructions;561
11.5.2;5.2 Unprivileged PALcode Instructions;599
11.5.3;5.3 Debug PALcode and Free PALcode;608
11.6;Chapter 6. Initialization and Firmware Transitions (II–C);610
11.6.1;6.1 Initialization;610
11.6.2;6.2 Firmware Interfaces;612
12;Part 5: Console Interface Architecture (III);616
12.1;Chapter 1. Console Subsystem Overview (III);622
12.1.1;1.1 Console Implementations;623
12.1.2;1.2 Console Implementation Registry;624
12.1.3;1.3 Console Presentation Layer;624
12.1.4;1.4 Messages;625
12.1.5;1.5 Security;625
12.1.6;1.6 Internationalization;625
12.2;Chapter 2. Console Interface to Operating System Software (III);628
12.2.1;2.1 Hardware Restart Parameter Block (HWRPB);628
12.2.2;2.2 Environment Variables;651
12.2.3;2.3 Console Callback Routines;656
12.2.4;2.4 Interprocessor Console Communications;698
12.3;Chapter 3. System Bootstrapping (III);702
12.3.1;3.1 Processor States and Modes;702
12.3.2;3.2 System Initialization;705
12.3.3;3.3 PALcode Loading and Switching;706
12.3.4;3.4 System Bootstrapping;710
12.3.5;3.5 System Restarts;728
12.3.6;3.6 Bootstrap Loading and Image Media Format;737
12.3.7;3.7 BB_WATCH;745
12.3.8;3.8 Implementation Considerations;747
13;Appendixes;750
14;Appendix A: Software Considerations;756
14.1;A.1 Hardware-Software Compact;756
14.2;A.2 Instruction-Stream Considerations;757
14.3;A.3 Data-Stream Considerations;761
14.4;A.4 Code Sequences;766
14.5;A.5 Timing Considerations: Atomic Sequences;772
15;Appendix B: IEEE Floating-Point Conformance;774
15.1;B.1 Alpha AXP Choices for IEEE Options;774
15.2;B.2 Alpha AXP Hardware Support of Software Exception Handlers;775
15.3;B.3 Mapping to IEEE Standard;778
16;Appendix C: Instruction Summary;786
16.1;C.1 Common Architecture Instruction Summary;786
16.2;C.2 IEEE Floating-Point Instructions;791
16.3;C.3 VAX Floating-Point Instructions;793
16.4;C.4 Opcode Summary;794
16.5;C.5 Common Architecture Opcodes in Numerical Order;796
16.6;C.6 OpenVMS AXP PALcode instruction Summary;800
16.7;C.7 DEC OSF/1 PALcode Instruction Summary;802
16.8;C.8 Windows NT AXP Instruction Summary;803
16.9;C.9 PALcode Opcodes in Numerical Order;805
16.10;C.10 Required PALcode Function Codes;808
16.11;C.11 Opcodes Reserved to PALcode;808
16.12;C.12 Opcodes Reserved to Digital;808
16.13;C.13 Unused Function Code Behavior;808
16.14;C.14 ASCII Character Set;810
17;Appendix D: Waivers and Implementation-Dependent Functionality;812
17.1;D.1 Waivers;812
17.2;D.2 Implementation-Specific Functionality;813
18;Index;830