Spiridon Toward 5G Software Defined Radio Receiver Front-Ends

1. Auflage 2016
ISBN: 978-3-319-32759-4
Verlag: Springer Nature Switzerland
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 112 Seiten

Reihe: SpringerBriefs in Electrical and Computer Engineering

This book introduces a new intuitive design methodology for the optimal design path for next-generation software defined radio front-ends (SDRXs). The methodology described empowers designers to 'attack' the multi-standard environment in a parallel way rather than serially, providing a critical tool for any design methodology targeting 5G circuits and systems. Throughout the book the SDRX design follows the key wireless standards of the moment (i.e., GSM, WCDMA, LTE, Bluetooth, WLAN), since a receiver compatible with these standards is the most likely candidate for the first design iteration in a 5G deployment. The author explains the fundamental choice the designer has to make regarding the optimal channel selection: how much of the blockers/interferers will be filtered in the analog domain and how much will remain to be filtered in the digital domain. The system-level analysis the author describes entails the direct sampling architecture is treated as a particular case of mixer-based direct conversion architecture. This allows readers give a power consumption budget to determine how much filtering is required on the receive path, by considering the ADC performance characteristics and the corresponding blocker diagram.

Dr. Silvian Spiridon (B.Sc.-2003, M.Sc.-2004 and Ph.D.-2011) is Principal Scientist with Broadcom Ltd. in Irvine, CA, USA. He is the project leader responsible for the design and development of wireline transceivers, high speed mixed-signal and RF circuits for cable applications. Dr. Spiridon is also a Senior Member with IEEE. His main research interest is focused on the development of a standard independent design methodology for wireless transceivers.

Autoren/Hrsg.

Spiridon, Silvian

Inhaltsverzeichnis

1;Foreword;10
2;Preface;14
3;Contents;16
4;Chapter 1: Overview of Wireless Communication in the Internet Age;19
4.1;1.1 Software Defined Radios;19
4.1.1;1.1.1 Digital Communications of the Internet Age;21
4.1.2;1.1.2 The Need for Software Defined Radios;24
4.1.3;1.1.3 The Software Defined Radio RF Front-End;26
4.2;1.2 Goals;27
4.3;1.3 Overview;28
4.4;References;29
5;Chapter 2: Defining the Optimal Architecture;31
5.1;2.1 Introduction;31
5.2;2.2 Overview of Receiver Architectures: Following the Image Rejection;32
5.2.1;2.2.1 Superheterodyne Receivers;32
5.2.1.1;Single Conversion;32
5.2.1.2;Dual or Double Conversion;34
5.2.2;2.2.2 Image Rejection Receivers;35
5.2.3;2.2.3 Direct Conversion Receivers;36
5.2.4;2.2.4 Low-IF Receivers;38
5.3;2.3 Final Decision: w/ IF vs. w/o IF (Zero-IF);38
5.3.1;2.3.1 Receiver Block Schematic;40
5.4;2.4 Making Direct Conversion Receivers Ready for Monolithic Integration;41
5.4.1;2.4.1 Key Issues;41
5.4.2;2.4.2 DC Offset Compensation;42
5.4.2.1;Static Offset Removal;42
5.4.2.2;Handling Dynamic Offset;43
5.4.3;2.4.3 Reducing Self-Mixing;44
5.4.4;2.4.4 Enhanced Receiver Schematic;44
5.4.5;2.4.5 Architectural Evolutions: Filter-Less and Mixer-Less Front-Ends;45
5.5;2.5 Conclusions;46
5.6;References;47
6;Chapter 3: From High-Level Standard Requirements to Circuit-Level Electrical Specifications: A Standard-Independent Approach;48
6.1;3.1 Multi-standard Environment Impact on the SDRX Building Block Features;48
6.1.1;3.1.1 Multiple Frequency Bands;48
6.1.2;3.1.2 Variable Channel Bandwidths;48
6.1.3;3.1.3 Different Burst Durations;50
6.1.4;3.1.4 Different Modulation Schemes and Techniques;50
6.2;3.2 Introducing the Minimum SNR for Proper Signal Demodulation;50
6.3;3.3 Deriving the SDRX Noise Figure;53
6.4;3.4 Generic Blocker Diagram;53
6.5;3.5 Blocker and Interferer Impact on the SDRX Linearity;54
6.5.1;3.5.1 Finding the SDRX IIP2;56
6.5.2;3.5.2 Finding the SDRX IIP3;58
6.6;3.6 LO Phase Noise Impact on the Receiver;59
6.7;3.7 Conclusion;60
6.8;References;61
7;Chapter 4: Optimal Filter Partitioning;62
7.1;4.1 Defining the Channel Selection Strategy;62
7.2;4.2 Deriving the ADC Specifications;63
7.3;4.3 The Optimal Trade-Off Between LPF Order and ADC Specifications;67
7.4;4.4 Conclusion;70
7.5;References;71
8;Chapter 5: Smart Gain Partitioning for Noise: Linearity Trade-Off Optimization;72
8.1;5.1 Proposed Gain-Noise-Linearity Partitioning Strategy;73
8.2;5.2 Defining the SDRX Gain Settings;75
8.3;5.3 Proposed Gain Partitioning Algorithm;78
8.4;5.4 The Automated Gain Control Loop;80
8.5;5.5 Conclusion;80
8.6;Reference;81
9;Chapter 6: SDRX Electrical Specifications;82
9.1;6.1 Electrical Specifications;82
9.2;6.2 Noise Partitioning;82
9.3;6.3 Linearity Partitioning;85
9.4;6.4 Conclusion;87
9.5;Reference;87
10;Chapter 7: A System-Level Perspective of Modern Receiver Building Blocks;88
10.1;7.1 SDRX HF Part Building Blocks;88
10.1.1;7.1.1 The Wideband Low-Noise Amplifier;88
10.1.2;7.1.2 The Highly Linear Downconversion Mixer;90
10.2;7.2 SDRX LF Part Building Blocks;92
10.2.1;7.2.1 The LF Part Building Brick: The Fully Differential Feedback Amplifier;92
10.2.2;7.2.2 LF Part Modular Architecture;94
10.2.3;7.2.3 FDFA Power Optimization;95
10.2.4;7.2.4 FDFA Opamp Generic Topology;97
10.3;7.3 SDRX Bias Block;98
10.4;7.4 Baseband Noise Partitioning;100
10.4.1;7.4.1 Noise Excess Factor;100
10.4.2;7.4.2 The Trade-Off Between LF Part Power Consumption and Area;102
10.4.3;7.4.3 Noise Partitioning;103
10.5;7.5 Conclusion;104
10.6;References;105
11;Chapter 8: Conclusions and Future Developments;107
11.1;8.1 Conclusions;107
11.2;8.2 Future Developments;110
11.3;References;111