Sterpone Electronics System Design Techniques for Safety Critical Applications

1. Auflage 2008
ISBN: 978-1-4020-8979-4
Verlag: Springer-Verlag
Format: PDF
Kopierschutz: Adobe DRM (»Systemvoraussetzungen)

E-Book, Englisch, 146 Seiten

What is exactly “Safety”? A safety system should be defined as a system that will not endanger human life or the environment. A safety-critical system requires utmost care in their specification and design in order to avoid possible errors in their implementation that should result in unexpected system’s behavior during his operating “life”. An inappropriate method could lead to loss of life, and will almost certainly result in financial penalties in the long run, whether because of loss of business or because the imposition of fines. Risks of this kind are usually managed with the methods and tools of the “safety engineering”. A life-critical system is designed to 9 lose less than one life per billion (10 ). Nowadays, computers are used at least an order of magnitude more in safety-critical applications compared to two decades ago. Increasingly electronic devices are being used in applications where their correct operation is vital to ensure the safety of the human life and the environment. These application ranging from the anti-lock braking systems (ABS) in automobiles, to the fly-by-wire aircrafts, to biomedical supports to the human care. Therefore, it is vital that electronic designers be aware of the safety implications of the systems they develop. State of the art electronic systems are increasingly adopting progr- mable devices for electronic applications on earthling system. In particular, the Field Programmable Gate Array (FPGA) devices are becoming very interesting due to their characteristics in terms of performance, dimensions and cost.

Autoren/Hrsg.

Sterpone, Luca

Inhaltsverzeichnis

1;CONTENTS;7
2;CONTRIBUTING AUTHOR;10
3;PREFACE;11
4;PART I;15
4.1;Chapter 1 AN INTRODUCTION TO FPGA DEVICES IN RADIATION ENVIRONMENTS;16
4.1.1;1. PREVIOUSLY DEVELOPED HARDENING TECHNIQUES;19
4.1.1.1;1.1 Reconfigurable-based techniques;20
4.1.1.2;1.2 Redundancy-based techniques;21
4.1.2;2. PRELIMINARIES OF SRAM-BASED FPGAS ARCHITECTURE;24
4.1.2.1;2.1 Generic SRAM-based FPGA model;24
4.1.2.2;2.2 FPGA routing graph;26
4.1.3;REFERENCES;28
4.2;Chapter 2 RADIATION EFFECTS ON SRAM-BASED FPGAS;29
4.2.1;1. RADIATION EFFECTS;30
4.2.1.1;1.1 Single Event Upset (SEU);31
4.2.1.2;1.2 Single Event Latch-Up (SEL);32
4.2.2;2. SEU EFFECTS ON FPGA’S CONFIGURATION MEMORY;33
4.2.3;3. SIMULATION-BASED ANALYSIS OF SEUs;35
4.2.3.1;3.1 Simulation environment;35
4.2.3.2;3.2 Fault simulation tool;38
4.2.3.3;3.3 Experimental results;40
4.2.4;4. HARDWARE-BASED ANALYSIS OF SEUs;42
4.2.4.1;4.1 Details on the Xilinx Triple Modular Redundancy;44
4.2.4.2;4.2 Analysis of TMR architecture;44
4.2.4.3;4.3 Experimental results;47
4.2.5;5. ROBUSTNESS OF THE TMR ARCHITECTURE;49
4.2.5.1;5.1 Analysis of the fault effects;51
4.2.6;6. CONSTRAINTS FOR ACHIEVING FAULT TOLERANCE;54
4.2.7;REFERENCES;55
4.3;Chapter 3 ANALYTICAL ALGORITHMS FOR FAULTY EFFECTS ANALYSIS;58
4.3.1;1. OVERVIEW ON STATIC ANALYSIS ALGORITHM;60
4.3.2;2. ANALYTICAL DEPENDABLE RULES;62
4.3.3;3. THE STAR ALGORITHM FOR SEU ANALYSIS;63
4.3.3.1;3.1 The dynamic evaluation platform;65
4.3.3.2;3.2 Experimental results of SEU static analysis;66
4.3.4;4. THE STAR ALGORITHM FOR MCU ANALYSIS;67
4.3.4.1;4.1 Analysis of errors produced by MCUs;69
4.3.4.2;4.2 Experimental results of MCU static analysis;78
4.3.5;REFERENCES;80
4.4;Chapter 4 RELIABILITY-ORIENTED PLACE AND ROUTE ALGORITHM;82
4.4.1;1. RoRA PLACEMENT ALGORITHM;84
4.4.2;2. RoRA ROUTING ALGORITHM;87
4.4.3;3. EXPERIMENTAL ANALYSIS;90
4.4.4;REFERENCES;93
4.5;Chapter 5 A NOVEL DESIGN FLOW FOR FAULT TOLERANCE SRAM- BASED FPGA SYSTEMS;95
4.5.1;1. THE DESIGN FLOW;97
4.5.1.1;1.1 STAR analyzer;98
4.5.1.2;1.2. RoRA router;99
4.5.2;2. PERFORMANCE OPTIMIZATION OF FAULT TOLERANT CIRCUITS;99
4.5.2.1;2.1 The congestion graph ;100
4.5.2.2;2.2 The voter architectures and arithmetic modules ;101
4.5.2.3;2.3 The V-Place algorithm;102
4.5.3;3. EXPERIMENTAL RESULTS;103
4.5.3.1;3.1 Timing analysis;104
4.5.3.2;3.2 Evaluating the proposed design flow;106
4.5.3.3;3.3 Evaluating a realistic circuit;107
4.5.4;REFERENCES;108
5;PART II;110
5.1;Chapter 6 CONFIGURATION SYSTEM BASED ON INTERNAL FPGA DECOMPRESSION;111
5.1.1;1. INTRODUCTION TO THE DECOMPRESSION SYSTEMS;111
5.1.2;2. OVERVIEW ON THE PREVIOUSLY DEVELOPED DECOMPRESSION SYSTEMS;113
5.1.2.1;2.1 Generalities of SRAM-based FPGAs;115
5.1.3;3. THE PROPOSED SYSTEM;116
5.1.4;4. EXPERIMENTAL RESULTS;119
5.1.4.1;4.1 Compression system results;120
5.1.5;REFERENCES;122
5.2;Chapter 7 RECONFIGURABLE DEVICES FOR THE ANALYSIS OF DNA MICROARRAY;124
5.2.1;1. INTRODUCTION TO THE DNA MICROARRAY;124
5.2.2;2. OVERVIEW ON THE PREVIOUSLY DEVELOPED ANALYSIS TECHNIQUES;126
5.2.3;3. PRELIMINARIES OF DNA MICROARRAY IMAGE ANALYSIS;128
5.2.3.1;3.1 The edge detection algorithm;129
5.2.4;4. THE PROPOSED DNA MICROARRAY ANALYSIS ARCHITECTURE;130
5.2.4.1;4.1 The edge detection architecture;132
5.2.4.2;4.2 The quality assessment core;135
5.2.5;5. EXPERIMENTAL RESULTS;136
5.2.6;REFERENCES;139
5.3;Chapter 8 RECONFIGURABLE COMPUTE FABRIC ARCHITECTURES;140
5.3.1;1. INTRODUCTION TO RCF DEVICES;141
5.3.2;2. THE ReCoM ARCHITECTURE;142
5.3.3;3. EXPERIMENTAL RESULTS;148
5.3.4;REFERENCES;149
6;Index;150