Stollon On-Chip Instrumentation

Design and Debug for Systems on Chip
1. Auflage 2010
ISBN: 978-1-4419-7563-8
Verlag: Springer-Verlag
Format: PDF
Kopierschutz: Wasserzeichen (»Systemvoraussetzungen)

E-Book, Englisch, 244 Seiten

This book provides an in-depth overview of on chip instrumentation technologies and various approaches taken in adding instrumentation to System on Chip (ASIC, ASSP, FPGA, etc.) design that are collectively becoming known as Design for Debug (DfD). On chip instruments are hardware based blocks that are added to a design for the specific purpose and improving the visibility of internal or embedded portions of the design (specific instruction flow in a processor, bus transaction in an on chip bus as examples) to improve the analysis or optimization capabilities for a SoC. DfD is the methodology and infrastructure that surrounds the instrumentation. Coverage includes specific design examples and discussion of implementations and DfD tradeoffs in a decision to design or select instrumentation or SoC that include instrumentation. Although the focus will be on hardware implementations, software and tools will be discussed in some detail.

Autoren/Hrsg.

Stollon, Neal

Inhaltsverzeichnis

1;Chapter 1: Introduction;11
1.1;1.1 The Need for On-Chip Debug;11
1.2;1.2 Instrument- (**in-silicon) and EDA- (Presilicon) Based Verification;13
1.3;1.3 SoC Debug Requirements;17
1.4;1.4 Instrumentation-Based Debug Infrastructure;21
2;Chapter 2: On-Chip Instrumentation Components;26
2.1;2.1 Trace and Event Triggering;26
2.2;2.2 External Interfaces for On-Chip Instrumentation;27
2.3;2.3 Performance Analysis Using On-Chip Instrumentation;28
2.4;2.4 On-Chip Logic and Bus Analysis;29
2.5;2.5 On-Chip Instrumentation Examples;31
2.5.1;2.5.1 Trace Monitoring and Interfaces;31
2.5.2;2.5.2 Bus Logic Monitoring;32
2.5.3;2.5.3 Real-Time Data Exchange;34
2.6;2.6 Multiprocessor Debug;35
3;Chapter 3: JTAG Use in Debug;40
3.1;3.1 JTAG Pins;41
3.2;3.2 Test Access Port;44
3.3;3.3 JTAG Registers;47
3.4;3.4 JTAG Instructions;48
3.5;3.5 Boundary-Scan Description Language;49
3.6;3.6 The Road to JTAG: Historical Debug Approaches;54
3.6.1;3.6.1 Background Debug Mode;56
4;Chapter 4: Processor System Debug;58
4.1;4.1 A Processor Debug Instrument Implementation;61
4.2;4.2 Processor Trace Compression;64
4.3;4.3 Hunting Code Errors with Self-Trace;68
5;Chapter 5: An On-Chip Debug System;70
5.1;5.1 OCDS Features;71
5.1.1;5.1.1 Debug Events;73
5.1.2;5.1.2 Debug Event Actions;73
5.1.3;5.1.3 Debug Registers;74
5.2;5.2 Operation Modes;74
5.2.1;5.2.1 Entering Communication Mode;75
5.2.2;5.2.2 Communication Mode Instructions;75
5.2.3;5.2.3 Monitor-to-Debugger Host Data Transfer (Receive);76
5.2.4;5.2.4 Debugger Host-to-Monitor Data Transfer (Send);76
5.2.5;5.2.5 High-Level Synchronization;76
5.3;5.3 OCDS Registers;77
5.3.1;5.3.1 Debug Task ID Register;77
5.3.2;5.3.2 Instruction Pointer Register;77
5.3.3;5.3.3 Hardware Trigger Comparison Registers;78
5.3.4;5.3.4 Considerations on Accessing OCDS Registers;78
5.4;5.4 OCDS JTAG Access;79
5.4.1;5.4.1 Steps to Initialize the JTAG Module;81
5.5;5.5 OCDS Module Access;81
5.5.1;5.5.1 Error Protection;81
5.6;5.6 OCDS JTAG I/O Instructions;83
5.7;5.7 OCDS JTAG Registers;85
5.8;5.8 Hardware Triggers;86
5.8.1;5.8.1 Structure of a Noninterruptible Monitor Routine;88
5.8.2;5.8.2 Structure of an Interruptible Monitor Routine;88
5.8.3;5.8.3 Debug Event Control Registers;89
5.9;5.9 Additional Features;90
5.9.1;5.9.1 System Security;91
5.9.2;5.9.2 Reset from the JTAG Side;92
5.9.3;5.9.3 Reset from the Chip/Processor Side;92
6;Chapter 6: Bus System Debug;93
6.1;6.1 On-Chip Buses;93
6.2;6.2 Socket-Based SoC Design;95
6.2.1;6.2.1 SoC Interconnect Complexities;95
6.3;6.3 Bus-Level Integration;98
6.3.1;6.3.1 Bus Master Monitoring;99
6.3.2;6.3.2 Peripheral Bus Monitoring;99
6.3.3;6.3.3 Slave Monitoring;99
6.4;6.4 Internal and External Alternatives for Bus Trace;100
6.5;6.5 Programmable Bus Performance Monitoring;101
6.6;6.6 Bus Performance Monitoring;102
6.7;6.7 On-Chip and Off-Chip Analysis;106
6.8;6.8 Request Response Trace Bus Analysis;109
6.8.1;6.8.1 RRT Operations;111
6.8.2;6.8.2 RRT Implementation;112
7;Chapter 7: Multiprocessor Debugging;116
7.1;7.1 Cross-Triggering and Global Breakpoint Control;117
7.2;7.2 HyperDebug Distributed Cross-Triggering;117
7.2.1;7.2.1 HyperDebug Controller;119
7.2.2;7.2.2 Typical HyperDebug Implementation;120
7.3;7.3 Multicore Synchronization Triggering and Global Actions;122
8;Chapter 8: IEEE 1149.7: cJTAG/aJTAG;123
8.1;8.1 Test and Debug Views of 1149.7;124
8.2;8.2 Key T0–T5 Class Functions;126
8.3;8.3 MIPI Use of 1149.7;135
8.3.1;8.3.1 MIPI System Trace Module;136
8.4;8.4 Nexus Use of 1149.7;138
8.4.1;8.4.1 IEEE 1149.7/Nexus Integration;140
9;Chapter 9: IEEE P1687 – IJTAG;142
9.1;9.1 Overlap Zones and Gateway Elements;144
9.2;9.2 Classes of P1687 Instruments;146
9.3;9.3 IEEE 1500 Instruments;148
10;Chapter 10: OCP IP Debug Interfaces;150
10.1;10.1 OCP Multicore Debug;151
10.2;10.2 OCP Debug Features;154
10.2.1;10.3.1 Pure Software Debugging;1
10.2.2;10.3.2 Pure Hardware Debugging;1
10.2.3;10.3.3 System-on-Chip Debugging;1
10.3;10.4 Debug Components and IP Interfaces;157
10.4;10.5 Debug Socket Definitions;157
10.4.1;10.5.1 Core Debug Socket Interfaces;159
10.4.2;10.5.2 Cross-Triggering Socket Interfaces;162
10.4.3;10.5.3 OCP Synchronized Run Control;166
10.4.4;10.5.4 OCP Traffic-Monitoring and Trace Interfaces;167
10.4.5;10.5.5 Performance Monitoring;169
10.4.6;10.5.6 System Timestamping;170
10.4.7;10.5.7 Power Management Monitoring;171
10.4.8;10.5.8 Security Debug Interface;172
11;Chapter 11: Nexus IEEE 5001;173
11.1;11.1 Nexus Implementation Classes;175
11.2;11.2 Nexus Message Architecture;176
11.2.1;11.2.1 Nexus TCODEs;178
11.2.2;11.2.2 Nexus Registers;182
11.3;11.3 NEXUS Interfaces;184
11.3.1;11.3.1 Nexus JTAG Access;184
11.3.2;11.3.2 NEXUS AUX Interfaces;185
11.4;11.4 Multicore Nexus Debug Approaches;189
11.4.1;11.4.1 Input Tool-to-Target Messages;191
11.4.2;11.4.2 Output Target-to-Tool Messages;192
11.5;11.5 Nexus Product Implementations;193
11.6;11.6 Summary;197
12;Chapter 12: MIPS EJTAG;198
12.1;12.1 EJTAG Instructions and Registers;200
12.2;12.2 PC Sampling;202
12.3;12.3 MIPS PDtrace™;202
12.3.1;12.3.1 Trace Output Formats;203
12.3.2;12.3.2 Trace Control Block Registers;207
12.4;12.4 TCB Trigger Logic Overview;209
12.5;12.5 PDtrace External Interface;210
12.6;12.6 TCtrace IF;212
12.7;12.7 PDTRACE Operations;213
13;Chapter 13: ARM ETM;215
13.1;13.1 ETM Signals;215
13.1.1;13.1.1 External Signals;216
13.2;13.2 ETM9 Registers;218
13.3;13.3 Trace Interface;220
14;Chapter 14: Infineon Multicore Debug Solution;221
14.1;14.1 MCDS Trace Protocol Definition;223
14.1.1;14.1.1 Data Trace;225
14.2;14.2 Debug Transactor: RUN Control Bus Master;226
14.3;14.3 MCDS Run Control: On-Chip Debug Support;227
14.3.1;14.3.1 BCU Level 1 (Bus-Observer Unit on the System Bus);229
14.3.2;14.3.2 Concurrent Debugging in Level 3 MCDS (Two-Channel Tracing);230
14.3.3;14.3.3 Debug Interface (Cerberus) (Debug Bus-Transactor Module);230
14.4;14.4 RW Mode and Communication Mode;230
14.5;14.5 Multicore Break Switch;231
15;Chapter 15: EJTAG and Trace in Toshiba TX Cores;233
15.1;15.1 Processor Access Overview;234
15.2;15.2 Toshiba EJTAG Instructions and Registers;235
15.3;15.3 Debug Exceptions;237
15.4;15.4 Processor Debug Instructions and CP0 Registers;237
15.5;15.5 Break Functions;239
15.6;15.6 Output by PC Trace;240
16;b978-0-387-78701_4;1