Tajalli / Leblebici Extreme Low-Power Mixed Signal IC Design

Subthreshold Source-Coupled Circuits
1. Auflage 2010
ISBN: 978-1-4419-6478-6
Verlag: Springer-Verlag
Format: PDF
Kopierschutz: Wasserzeichen (»Systemvoraussetzungen)

E-Book, Englisch, 274 Seiten

Design exibility and power consumption in addition to the cost, have always been the most important issues in design of integrated circuits (ICs), and are the main concerns of this research, as well. Energy Consumptions: Power dissipation (P ) and energy consumption are - diss pecially importantwhen there is a limited amountof power budgetor limited source of energy. Very common examples are portable systems where the battery life time depends on system power consumption. Many different techniques have been - veloped to reduce or manage the circuit power consumption in this type of systems. Ultra-low power (ULP) applications are another examples where power dissipation is the primary design issue. In such applications, the power budget is so restricted that very special circuit and system level design techniquesare needed to satisfy the requirements. Circuits employed in applications such as wireless sensor networks (WSN), wearable battery powered systems [1], and implantable circuits for biol- ical applications need to consume very low amount of power such that the entire system can survive for a very long time without the need for changingor recharging battery[2-4]. Using newpowersupplytechniquessuchas energyharvesting[5]and printable batteries [6], is another reason for reducing power dissipation. Devel- ing special design techniques for implementing low power circuits [7-9], as well as dynamic power management (DPM) schemes [10] are the two main approaches to control the system power consumption. Design Flexibility: Design exibility is the other important issue in modern in- grated systems.

Autoren/Hrsg.

Tajalli, Armin

Leblebici, Yusuf

Inhaltsverzeichnis

1;Extreme Low-Power Mixed Signal IC Design;3
1.1;Contents;7
1.2;List of Figures;13
1.3;List of Tables;27
1.4;Acknowledgments;29
1.5;Acronyms;31
1.6;Chapter 1: Introduction;35
1.6.1;1.1 Applications of Widely Adjustable Circuits and Systems;36
1.6.1.1;1.1.1 Performance Scalability and Requirements;39
1.6.2;1.2 Prior Art;40
1.6.2.1;1.2.1 Digital Circuits;40
1.6.2.1.1;1.2.1.1 Static CMOS Logic;40
1.6.2.1.2;1.2.1.2 Other Logic Styles;41
1.6.2.2;1.2.2 Analog Circuits;42
1.6.2.2.1;1.2.2.1 Circuits Using Switchable (Programmable) Components;42
1.6.2.2.2;1.2.2.2 Switched-Capacitor Circuits;43
1.6.2.2.3;1.2.2.3 Log-Domain Circuits;44
1.6.3;1.3 Organization;44
1.6.4;References;45
1.7;Chapter 2: Subthreshold MOS for Ultra-Low Power;48
1.7.1;2.1 MOS Technology;48
1.7.2;2.2 Device Modeling;49
1.7.2.1;2.2.1 I–V Characteristics;49
1.7.2.2;2.2.2 Second Order Effects;52
1.7.2.2.1;2.2.2.1 Mobility Reduction Due to Vertical Field;52
1.7.2.2.2;2.2.2.2 Velocity Saturation;53
1.7.2.2.3;2.2.2.3 Channel Length Modulation;53
1.7.3;2.3 Design Considerations in Subthreshold;54
1.7.3.1;2.3.1 PVT Variation;54
1.7.3.2;2.3.2 Matching;56
1.7.3.2.1;2.3.2.1 Physical Mechanism of VT Fluctuation;57
1.7.3.2.2;2.3.2.2 Mismatch due to Gate Leakage;58
1.7.3.3;2.3.3 Noise;59
1.7.3.3.1;2.3.3.1 Noise Efficiency Factor;60
1.7.3.3.2;2.3.3.2 Noise Due to the Gate Leakage;61
1.7.4;2.4 Ultra-Low-Power Design Using Subthreshold MOS;62
1.7.4.1;2.4.1 MOS Transistor Leakage Mechanisms;63
1.7.4.1.1;2.4.1.1 Scaling Rules;63
1.7.4.1.2;2.4.1.2 Gate Tunneling;64
1.7.4.1.3;2.4.1.3 Subthreshold Conducting;65
1.7.4.1.4;2.4.1.4 PN Junction;65
1.7.4.1.5;2.4.1.5 DIBL;66
1.7.4.1.6;2.4.1.6 GIDL;67
1.7.4.1.7;2.4.1.7 Hot Carrier;68
1.7.4.1.8;2.4.1.8 Punchthrough;68
1.7.4.1.9;2.4.1.9 Channel Length Effect;68
1.7.4.1.10;2.4.1.10 Narrow-Width Effect;68
1.7.4.1.11;2.4.1.11 Thermal Effect;68
1.7.4.1.12;2.4.1.12 Short Circuit Current;69
1.7.4.2;2.4.2 Leakage Reduction Techniques;69
1.7.4.2.1;2.4.2.1 Device Level Engineering;69
1.7.4.2.2;2.4.2.2 Circuit Level Techniques;69
1.7.5;2.5 Impacts of Variation on Subthreshold CMOS Operation;70
1.7.5.1;2.5.1 Noise Margin;72
1.7.5.2;2.5.2 Energy Consumption;78
1.7.5.3;2.5.3 Optimal Design with Technology Scaling;82
1.7.5.3.1;2.5.3.1 A Low Activity Rate System Example;82
1.7.5.3.2;2.5.3.2 A High Activity Rate System Example;84
1.7.5.3.3;2.5.3.3 Discussion;85
1.7.5.4;2.5.4 Supply Voltage and Threshold Voltage Scaling for Optimal Design;86
1.7.6;References;89
1.8;Part I Scalable and Ultra-Low-Power Digital Integrated Circuits;92
1.8.1;Chapter:3: Subthreshold Source-Coupled Logic;93
1.8.1.1;3.1 Introduction;93
1.8.1.2;3.2 Conventional SCL Topology;95
1.8.1.2.1;3.2.1 Circuit Topology;95
1.8.1.2.2;3.2.2 Tradeoffs in Design of Strong-Inversion SCL Gates;99
1.8.1.3;3.3 Ultra-Low-Power Source-Coupled Logic;102
1.8.1.3.1;3.3.1 High-Valued Load Device Concept;102
1.8.1.3.1.1;3.3.1.1 DC Characteristics of the Load Devices;104
1.8.1.3.1.2;3.3.1.2 Floating High-Valued Resistance;106
1.8.1.3.2;3.3.2 STSCL Gates;106
1.8.1.4;3.4 Design Issues and Performance Estimation;108
1.8.1.4.1;3.4.1 Power-Speed Tradeoffs in STSCL;108
1.8.1.4.2;3.4.2 Noise Margin;111
1.8.1.4.3;3.4.3 Replica Bias Circuit;115
1.8.1.4.4;3.4.4 Minimum Operating Current;116
1.8.1.4.5;3.4.5 Global Process and Temperature Variation;118
1.8.1.4.6;3.4.6 Effect of Mismatch on Delay;119
1.8.1.4.7;3.4.7 Minimum Supply Voltage;121
1.8.1.5;3.5 Experimental Results;121
1.8.1.5.1;3.5.1 Basic Building Blocks;121
1.8.1.5.2;3.5.2 Ring Oscillator and Frequency Divider;122
1.8.1.5.2.1;3.5.2.1 Ring Oscillator Test Circuit;123
1.8.1.5.2.2;3.5.2.2 Divider Test Circuit;124
1.8.1.5.3;3.5.3 Multiplier Circuit;126
1.8.1.6;3.6 Conclusion;127
1.8.1.7;References;128
1.8.2;Chapter 4: STSCL Standard Cell Library Development;130
1.8.2.1;4.1 Introduction;130
1.8.2.2;4.2 Standard Cell Library;131
1.8.2.2.1;4.2.1 Background;131
1.8.2.2.2;4.2.2 Cell Types;132
1.8.2.2.3;4.2.3 Cell Layout;132
1.8.2.2.4;4.2.4 Characterization;134
1.8.2.2.5;4.2.5 LEF File;135
1.8.2.2.6;4.2.6 Template Generation;135
1.8.2.3;4.3 Design Strategies;136
1.8.2.3.1;4.3.1 Series–Parallel Tail Bias Transistors;137
1.8.2.3.2;4.3.2 Constant Area Scaling;138
1.8.2.4;4.4 Demonstration Circuits;139
1.8.2.4.1;4.4.1 FIR Filter Topology;139
1.8.2.4.2;4.4.2 Sample FIR Filter Demonstrator Circuit;140
1.8.2.4.2.1;4.4.2.1 FIR Filter in CMOS 0.18m;140
1.8.2.4.2.2;4.4.2.2 FIR Filter in CMOS 90nm;142
1.8.2.5;4.5 Conclusion;143
1.8.2.6;References;144
1.8.3;Chapter 5: Subthreshold Source-Coupled Logic Performance Analysis;145
1.8.3.1;5.1 Introduction;145
1.8.3.2;5.2 Comparison with the CMOS Topology;146
1.8.3.2.1;5.2.1 Ultra-Low-Power Requirements;146
1.8.3.2.2;5.2.2 Power-Speed Tradeoff in STSCL;147
1.8.3.2.3;5.2.3 Performance Analysis of CMOS Logic Circuits;148
1.8.3.2.4;5.2.4 Performance Comparison;151
1.8.3.3;5.3 Performance Improvement Techniques;152
1.8.3.3.1;5.3.1 Compound Logic Style;153
1.8.3.3.2;5.3.2 Using Source-Follower Buffer;155
1.8.3.3.2.1;5.3.2.1 Proposed Topology;155
1.8.3.3.2.2;5.3.2.2 Performance Analysis;156
1.8.3.3.2.3;5.3.2.3 Optimized Design;159
1.8.3.3.3;5.3.3 Pipelining Technique;160
1.8.3.4;5.4 Experimental Results;163
1.8.3.4.1;5.4.1 STSCL with Source-Follower Buffer;163
1.8.3.4.2;5.4.2 Pipelined Adder Chain;164
1.8.3.4.3;5.4.3 Pipelined Multiplier;165
1.8.3.5;5.5 Conclusions;167
1.8.3.6;References;168
1.8.4;Chapter 6: Low-Activity-Rate and Memory Circuits in STSCL;170
1.8.4.1;6.1 Introduction;170
1.8.4.2;6.2 Power Efficiency in Low Activity Rates;171
1.8.4.2.1;6.2.1 STSCL Topology Performance;171
1.8.4.2.2;6.2.2 CMOS Topology Performance;173
1.8.4.2.3;6.2.3 Comparison;174
1.8.4.3;6.3 Low-Leakage CMOS SRAMs;175
1.8.4.4;6.4 Low Stand-By Current STSCL Memory Cell;178
1.8.4.4.1;6.4.1 Circuit Topology;178
1.8.4.4.2;6.4.2 Device Sizing;180
1.8.4.4.3;6.4.3 Sense Amplifier;181
1.8.4.4.4;6.4.4 Leakage Current Detection;182
1.8.4.5;6.5 Experimental Results;182
1.8.4.6;6.6 Observations and Discussion;185
1.8.4.7;References;186
1.9;Part II Scalable and Ultra-Low-Power Analog Integrated Circuits;188
1.9.1;Chapter 7: Widely Adjustable Continuous-Time Filter Design;189
1.9.1.1;7.1 Introduction;189
1.9.1.2;7.2 Amplifier Design;190
1.9.1.2.1;7.2.1 Low Power Folded-Cascode Amplifier;190
1.9.1.2.2;7.2.2 Widely Adjustable Two-Stage Amplifier;192
1.9.1.3;7.3 Transconductor-C Filter Design;194
1.9.1.3.1;7.3.1 Proposed Biquadratic Filter Topology;194
1.9.1.3.1.1;7.3.1.1 Proposed Circuit Topology;195
1.9.1.3.2;7.3.2 Dynamic Range;198
1.9.1.3.3;7.3.3 Sixth Order gm-C Filter;199
1.9.1.4;7.4 MOSFET-C Filter Design;199
1.9.1.4.1;7.4.1 Circuit Topology;200
1.9.1.4.2;7.4.2 High-Valued Pseudo-Resistance;200
1.9.1.4.3;7.4.3 Dynamic Range;203
1.9.1.4.4;7.4.4 Second Order MOSFET-C Filter;205
1.9.1.5;7.5 Experimental Results;206
1.9.1.5.1;7.5.1 MOSFET-C Filter;206
1.9.1.5.2;7.5.2 gm-C Filter;208
1.9.1.5.3;7.5.3 Figure of Merit;210
1.9.1.6;7.6 Conclusion;211
1.9.1.7;References;212
1.9.2;Chapter 8: Scalable Folding and Interpolating ADC Design;214
1.9.2.1;8.1 Introduction;214
1.9.2.2;8.2 Previous Art;214
1.9.2.3;8.3 Folding and Interpolating Analog-to-Digital Converter;216
1.9.2.3.1;8.3.1 Basics;216
1.9.2.3.1.1;8.3.1.1 Nonideality Effects in FAI ADCs;218
1.9.2.3.2;8.3.2 Building Blocks and Design Tradeoffs;219
1.9.2.3.2.1;8.3.2.1 Resistor Ladder;219
1.9.2.3.2.2;8.3.2.2 Offset Effect on Linearity;221
1.9.2.3.2.3;8.3.2.3 Offset Effect on Speed and Power;224
1.9.2.4;8.4 Design of FAI ADC;225
1.9.2.4.1;8.4.1 Circuit Topology;226
1.9.2.4.2;8.4.2 Ultra Low Power Resistor Ladder;229
1.9.2.4.3;8.4.3 Comparator Circuit;231
1.9.2.4.4;8.4.4 Encoder;233
1.9.2.5;8.5 Simulation and Experimental Results;236
1.9.2.5.1;8.5.1 Encoder;236
1.9.2.5.2;8.5.2 FAI ADC Performance;237
1.9.2.6;8.6 Conclusion;238
1.9.2.7;References;239
1.9.3;Chapter 9: Widely Adjustable Ring Oscillator Based ADC;241
1.9.3.1;9.1 Introduction;241
1.9.3.2;9.2 Background;241
1.9.3.2.1;9.2.1 Dynamic Range;241
1.9.3.2.2;9.2.2 Improving the Resolution;243
1.9.3.3;9.3 Performance Scalability in Ring Oscillator Based ADCs;244
1.9.3.3.1;9.3.1 Frequency Domain Adjustability;244
1.9.3.3.2;9.3.2 Dynamic Range Adjustment;248
1.9.3.4;9.4 Top Level Design;249
1.9.3.4.1;9.4.1 Sources of Non-Ideality;249
1.9.3.4.1.1;9.4.1.1 Delay Mismatch;249
1.9.3.4.1.2;9.4.1.2 Ring Oscillator Jitter;250
1.9.3.4.1.3;9.4.1.3 Sampling Clock Jitter;250
1.9.3.4.1.4;9.4.1.4 Comparator Meta-Stability Effect;251
1.9.3.4.2;9.4.2 Performance Analysis;252
1.9.3.5;9.5 Circuit Design;254
1.9.3.5.1;9.5.1 Ring Oscillator;254
1.9.3.5.1.1;9.5.1.1 Delay Matching;254
1.9.3.5.1.2;9.5.1.2 Oscillator Jitter;256
1.9.3.5.2;9.5.2 Logic Circuit;257
1.9.3.5.3;9.5.3 Current-Mode Integrator;257
1.9.3.6;9.6 High Order Modulator Design;259
1.9.3.6.1;9.6.1 Analysis and Modeling;259
1.9.3.6.2;9.6.2 Behavioral Modeling;263
1.9.3.7;9.7 Simulations and Experimental Results;266
1.9.3.8;9.8 Conclusion and Discussion;267
1.9.3.9;References;268
1.9.4;Chapter 10: Wide Tuning Range PLL;269
1.9.4.1;10.1 Introduction;269
1.9.4.2;10.2 Wide Tuning Range PLLs;269
1.9.4.2.1;10.2.1 Background;270
1.9.4.2.2;10.2.2 Wide Tuning Range CPLL;272
1.9.4.2.3;10.2.3 Design Issues with Wide Tune PLLs;275
1.9.4.3;10.3 Circuit Design;276
1.9.4.3.1;10.3.1 Proposed PLL Topology;276
1.9.4.3.2;10.3.2 Ring Oscillator;278
1.9.4.3.3;10.3.3 Frequency Divider and Phase-Frequency Detector (PFD);279
1.9.4.3.4;10.3.4 Transconductor;280
1.9.4.4;10.4 Simulation and Experimental Results;280
1.9.4.5;10.5 Conclusions;284
1.9.4.6;References;284
1.9.5;Chapter 11: Conclusions;286
1.9.5.1;11.1 Main Contributions;287
1.9.5.2;11.2 Perspectives;289
1.9.5.3;References;290
1.9.6;Index;292