Takano | Thinking Machines | E-Book | sack.de
E-Book

E-Book, Englisch, 322 Seiten

Takano Thinking Machines

Machine Learning and Its Hardware Implementation
1. Auflage 2021
ISBN: 978-0-12-818280-2
Verlag: Elsevier Science & Techn.
Format: EPUB
Kopierschutz: 6 - ePub Watermark

Machine Learning and Its Hardware Implementation

E-Book, Englisch, 322 Seiten

ISBN: 978-0-12-818280-2
Verlag: Elsevier Science & Techn.
Format: EPUB
Kopierschutz: 6 - ePub Watermark



Thinking Machines: Machine Learning and Its Hardware Implementation covers the theory and application of machine learning, neuromorphic computing and neural networks. This is the first book that focuses on machine learning accelerators and hardware development for machine learning. It presents not only a summary of the latest trends and examples of machine learning hardware and basic knowledge of machine learning in general, but also the main issues involved in its implementation. Readers will learn what is required for the design of machine learning hardware for neuromorphic computing and/or neural networks.This is a recommended book for those who have basic knowledge of machine learning or those who want to learn more about the current trends of machine learning. - Presents a clear understanding of various available machine learning hardware accelerator solutions that can be applied to selected machine learning algorithms - Offers key insights into the development of hardware, from algorithms, software, logic circuits, to hardware accelerators - Introduces the baseline characteristics of deep neural network models that should be treated by hardware as well - Presents readers with a thorough review of past research and products, explaining how to design through ASIC and FPGA approaches for target machine learning models - Surveys current trends and models in neuromorphic computing and neural network hardware architectures - Outlines the strategy for advanced hardware development through the example of deep learning accelerators

Shigeyuki Takano received a BEEE from Nihon University, Tokyo, Japan and an MSCE from the University of Aizu, Aizuwakamatsu, Japan. He is currently a PhD student of CSE at Keio University, Tokyo, Japan. He previously worked for a leading automotive company and, currently, he is working for a leading high-performance computing company. His research interests include computer architectures, particularly coarse-grained reconfigurable architectures, graph processors, and compiler infrastructures.

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